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== Overview ==
 
== Overview ==
 
The ARMv2 is the second iteration of the ARM instruction set which was introduced with [[Acorn]]'s {{acorn|ARM2|l=arch}} in 1986. The ARMv2 added support for multiplication and a coprocessor communication interface. It also adds two additional status registers for a total of 27 registers.
 
The ARMv2 is the second iteration of the ARM instruction set which was introduced with [[Acorn]]'s {{acorn|ARM2|l=arch}} in 1986. The ARMv2 added support for multiplication and a coprocessor communication interface. It also adds two additional status registers for a total of 27 registers.
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== New Instructions ==
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ARMv2 adds a number of new instructions:
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* [[#movement_instructions|Movement Instructions]]
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* [[#load_instructions|Load Instructions]]
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* [[#store_instructions|Store Instructions]]
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* [[#arithmetic_instructions|Arithmetic Instructions]]
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* [[#coprocessor_instructions|Coprocessor Instructions]]
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{{isa
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| title    = New ARMv2 ISA Instructions
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| Syntax
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| Description
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| Action
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| cols = 5
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| listing  =
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{{inst|cols=5|section=<span id="movement_instructions">'''Movement Instructions'''</span><br><small>Movement instructions move data between registers and operands.</small>}}
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{{inst|mn=MCR |col 1=MCR<cond> <copro>, <op1>, Rd, Cn, Cm {, <op2>} |col 2=Move to Coprocessor register  |col 3 = Coprocessor <copro> = Rd}}
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{{inst|mn=MRC |col 1=MRC<cond> <copro>, <op1>, Rd, Cn, Cm , <op2>  |col 2=Move register from a Coprocessor  |col 3 = Rd = Coprocessor <copro>}}
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{{inst|cols=5|section=<span id="load_instructions">'''Load Instructions'''</span><br><small>Load instructions move the content of memory addresses into registers.</small>}}
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{{inst|mn=LDC |col 1=LDC<cond>{L} <copro>, Cd, [Rn {, #imm * 4}]{!}  |col 2=Load to Coprocessor  |col 3 = Coprocessor <copro> = [Rn + imm]<br>If !: Rn = Rn + imm}}
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{{inst|mn=LDC |col 1=LDC<cond>{L} <copro>, Cd, [Rn], #{-}<immed8> * 4 |col 2=Load to Coprocessor  |col 3 = Coprocessor <copro> = [Rn + imm]<br>Rn = Rn + imm }}
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{{inst|mn=LDC |col 1=LDC<cond>{L} <copro>, Cd, [Rn], <option>        |col 2=Load to Coprocessor  |col 3 = Coprocessor <copro> = [Rn] }}
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{{inst|cols=5|section=<span id="store_instructions">'''Store Instructions'''</span><br><small>Store instructions moves the values from registers into memory.</small>}}
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{{inst|mn=STC |col 1=STC<cond>{L} <copro>, Cd, [Rn {, #imm * 4}]{!}  |col 2=Store from Coprocessor  |col 3 = [Rn + imm] = Coprocessor <copro><br>If !: Rn = Rn + imm}}
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{{inst|mn=STC |col 1=STC<cond>{L} <copro>, Cd, [Rn], #{-}<immed8> * 4 |col 2=Store from Coprocessor  |col 3 = [Rn + imm] = Coprocessor <copro><br>Rn = Rn + imm }}
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{{inst|mn=STC |col 1=STC<cond>{L} <copro>, Cd, [Rn], <option>        |col 2=Store from Coprocessor  |col 3 = [Rn] = Coprocessor <copro> }}
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{{inst|cols=5|section=<span id="coprocessor_instructions">'''Coprocessor Instructions'''</span><br><small>Operates on a Coprocessor.</small>}}
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{{inst|mn=CDP |col 1=CDP<cond> <copro>, <op1>, Cd, Cn, Cm, <op2>      |col 2=Coprocessor Data Process  |col 3 = Execut OP Given on Coprocessor <copro>}}
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{{inst|cols=5|section=<span id="arithmetic_instructions">'''Arithmetic Instructions'''</span><br><small>Arithmetic instructions perform basic mathematical operations on two operands.</small>}}
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{{inst|mn=MLA |col 1=MLA<cond>{S} Rd, Rm, Rs, Rn  |col 2=Multiply and accumulate  |col 3 =Rd = (Rm * Rs) + Rn}}
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{{inst|mn=MUL |col 1=MUL<cond>{S} Rd, Rm, Rs      |col 2=Multiply                |col 3 =Rd = Rm * Rs}}
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}}

Latest revision as of 20:30, 10 July 2017

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ARMv2 is the second ARM instruction set version which was introduced by Acorn with the release of the ARM2 in 1986. The ARMv2 was the first instruction set to be used commercially.

Overview[edit]

The ARMv2 is the second iteration of the ARM instruction set which was introduced with Acorn's ARM2 in 1986. The ARMv2 added support for multiplication and a coprocessor communication interface. It also adds two additional status registers for a total of 27 registers.

New Instructions[edit]

ARMv2 adds a number of new instructions:

New ARMv2 ISA Instructions
Mnemonic Syntax Description Action
Movement Instructions
Movement instructions move data between registers and operands.
MCRMCR<cond> <copro>, <op1>, Rd, Cn, Cm {, <op2>}Move to Coprocessor registerCoprocessor <copro> = Rd
MRCMRC<cond> <copro>, <op1>, Rd, Cn, Cm , <op2>Move register from a CoprocessorRd = Coprocessor <copro>
Load Instructions
Load instructions move the content of memory addresses into registers.
LDCLDC<cond>{L} <copro>, Cd, [Rn {, #imm * 4}]{!}Load to CoprocessorCoprocessor <copro> = [Rn + imm]
If !: Rn = Rn + imm
LDCLDC<cond>{L} <copro>, Cd, [Rn], #{-}<immed8> * 4Load to CoprocessorCoprocessor <copro> = [Rn + imm]
Rn = Rn + imm
LDCLDC<cond>{L} <copro>, Cd, [Rn], <option>Load to CoprocessorCoprocessor <copro> = [Rn]
Store Instructions
Store instructions moves the values from registers into memory.
STCSTC<cond>{L} <copro>, Cd, [Rn {, #imm * 4}]{!}Store from Coprocessor[Rn + imm] = Coprocessor <copro>
If !: Rn = Rn + imm
STCSTC<cond>{L} <copro>, Cd, [Rn], #{-}<immed8> * 4Store from Coprocessor[Rn + imm] = Coprocessor <copro>
Rn = Rn + imm
STCSTC<cond>{L} <copro>, Cd, [Rn], <option>Store from Coprocessor[Rn] = Coprocessor <copro>
Coprocessor Instructions
Operates on a Coprocessor.
CDPCDP<cond> <copro>, <op1>, Cd, Cn, Cm, <op2>Coprocessor Data ProcessExecut OP Given on Coprocessor <copro>
Arithmetic Instructions
Arithmetic instructions perform basic mathematical operations on two operands.
MLAMLA<cond>{S} Rd, Rm, Rs, RnMultiply and accumulateRd = (Rm * Rs) + Rn
MULMUL<cond>{S} Rd, Rm, RsMultiplyRd = Rm * Rs
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