Semiconductor & Computer Engineering
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Difference between revisions of "arm/armv1"
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== Overview == | == Overview == | ||
| − | The ARMv1 is a simple architecture. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a [[program counter]] | + | The ARMv1 is a simple architecture consisting of mostly simple operations along with a handful of complex ones. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a 24-bit [[program counter]] allowing for a 26-bit address space of up to 64 MiB of memory. |
== Registers == | == Registers == | ||
Revision as of 19:38, 27 June 2017
ARMv1 is the first ARM instruction set version. Introduced with the ARM1 on April 26 1985, the ARMv1 defines a 32-bit ISA along with 26-bit addressing space. The ARMv1 was only implemented by the ARM1 and was replaced soon after by the ARM2. Only a few hundred of those chips were ever fabricated.
Overview
The ARMv1 is a simple architecture consisting of mostly simple operations along with a handful of complex ones. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a 24-bit program counter allowing for a 26-bit address space of up to 64 MiB of memory.
Registers
There are 16 general purpose 32-bit registers. With the exception of register 15, all registers are orthogonal with no specific designated purpose.
Instruction Listing
The ARMv1 is broken down into 8 classes of instruction:
- Movement Instructions
- Load Instructions
- Store Instructions
- Arithmetic Instructions
- Logical Instructions
- Comparison Instructions
- Branch Instructions
- Miscellaneous Instructions
| ARMv1 ISA | ||||
|---|---|---|---|---|
| Mnemonic | Syntax | Description | Action | |
| Movement Instructions | ||||
| MOV | MOV<cond>{S} Rd, #imm | Move value immed | Rd = immed | |
| MOV | MOV<cond>{S} Rd, Rm, {, <shift>} | Move value | Rd = {shifted Rm} | |
| MVN | MVN<cond>{S} Rd, #imm | Move NOT value immed | Rd = ¬immed | |
| MVN | MVN<cond>{S} Rd, Rm, {, <shift>} | Move NOT value | Rd = ¬{shifted Rm} | |
| Load Instructions | ||||
| LDM | LDM<cond><type> Rn{!}, <reglist>{^} | Load multiple | addr = Rn for each Rd in {reglist}: Rd = [addr] update address based on {type} | |
| LDR | LDR<cond>{B} Rd, [Rn {, #imm}]{!} | Load register immed | Rd = [Rn + imm] If !: Rn = Rn + imm | |
| LDR | LDR<cond>{B} Rd, [Rn, Rm {, <shift>}]{!} | Load register | Rd = [Rn + {shifted Rm}] If !: Rn = Rn + {shifted Rm}] | |
| LDR | LDR<cond>{B}{T} Rd, [Rn], #imm | Load register, post index | Rd = [Rn] Rn = Rn + imm | |
| LDR | LDR<cond>{B}{T} Rd, [Rn], Rm {, <shift>} | Load register, post index | Rd = [Rn] Rn = Rn + {shifted Rm} | |
| Store Instructions | ||||
| STM | STM<cond><type> Rn{!}, <reglist>{^} | Store multiple | addr = Rn for each Rd in {reglist}: [addr] = Rd update address based on {type} | |
| STR | STR<cond>{B} Rd, [Rn {, #imm}]{!} | Store register immed | [Rn + imm] = Rd If !: Rn = Rn + imm | |
| STR | STR<cond>{B} Rd, [Rn, Rm {, <shift>}]{!} | Store register | [Rn + {shifted Rm}] = Rd If !: Rn = Rn + {shifted Rm}] | |
| STR | STR<cond>{B}{T} Rd, [Rn], #imm | Store register, post index | [Rn] = Rd Rn = Rn + imm | |
| STR | STR<cond>{B}{T} Rd, [Rn], Rm {, <shift>} | Store register, post index | [Rn] = Rd Rn = Rn + {shifted Rm} | |
| Arithmetic Instructions | ||||
| ADC | ADC<cond>{S} Rd, Rn, #imm | Add and carry immed | Rd = Rn + imm + C | |
| ADC | ADC<cond>{S} Rd, Rn, Rm{, <shift>} | Add and carry | Rd = Rn + {shifted Rm} + C | |
| ADD | ADD<cond>S Rd, Rn, #imm | Add immed | Rd = Rn + imm | |
| ADD | ADD<cond>S Rd, Rn, Rm{, <shift>} | Add | Rd = Rn + {shifted Rm} | |
| RSB | RSB<cond>S Rd, Rn, #imm | Reverse subtract immed | Rd = imm - Rn | |
| RSB | RSB<cond>S Rd, Rn, Rm{, <shift>} | Reverse subtract | Rd = {shifted Rm} - Rn | |
| RSC | RSB<cond>S Rd, Rn, #imm | Reverse subtract with carry immed | Rd = imm - Rn - ¬C | |
| RSC | RSB<cond>S Rd, Rn, Rm{, <shift>} | Reverse subtract with carry | Rd = {shifted Rm} - Rn - ¬C | |
| SBC | SBC<cond>{S} Rd, Rn, #imm | Subtract with carry immed | Rd = Rn - imm - ¬C | |
| SBC | SBC<cond>{S} Rd, Rn, Rm{, <shift>} | Subtract with carry | Rd = Rn - {shifted Rm} - ¬C | |
| SUB | SUB<cond>{S} Rd, Rn, #imm | Subtract immed | Rd = Rn - imm | |
| SUB | SUB<cond>{S} Rd, Rn, Rm{, <shift>} | Subtract | Rd = Rn - {shifted Rm} | |
| Logical Instructions | ||||
| AND | AND<cond>{S} Rd, Rn, #imm | AND immed | Rd = Rn & imm | |
| AND | AND<cond>{S} Rd, Rn, Rm{, <shift>} | AND | Rd = Rn & {shifted Rm} | |
| BIC | BIC<cond>{S} Rd, Rn, #imm | Bit clear immed | Rd = Rn & ¬imm | |
| BIC | BIC<cond>{S} Rd, Rn, Rm{, <shift>} | Bit clear | Rd = Rn & ¬Rm | |
| EOR | EOR<cond>{S} Rd, Rn, #imm | Exclusive OR immed | Rd = Rn ⊕ imm | |
| EOR | EOR<cond>{S} Rd, Rn, Rm{, <shift>} | Exclusive OR | Rd = Rn ⊕ {shifted Rm} | |
| ORR | ORR<cond>{S} Rd, Rn, #imm | Logical OR immed | Rd = Rn ∥ imm | |
| ORR | ORR<cond>{S} Rd, Rn, Rm{, <shift>} | Logical OR | Rd = Rn ∥ {shifted Rm} | |
| Comparison Instructions | ||||
| CMN | CMN<cond> Rn, #imm | Compare negative immed | CPSR flags set on (Rn + imm) | |
| CMN | CMN<cond> Rn, Rm{, <shift>} | Compare negative | CPSR flags set on (Rn + {shifted Rm}) | |
| CMP | CMP<cond> Rn, #imm | Compare immed | CPSR flags set on (Rn - imm) | |
| CMP | CMP<cond> Rn, Rm{, <shift>} | Compare | CPSR flags set on (Rn - {shifted Rm}) | |
| TEQ | TEQ<cond> Rn, #imm | Test equality immed | CPSR flags set on (Rn ⊕ imm) | |
| TEQ | TEQ<cond> Rn, Rm{, <shift>} | Test equality | CPSR flags set on (Rn ⊕ {shifted Rm}) | |
| TST | TST<cond> Rn, #imm | Test bits immed | CPSR flags set on (Rn & imm) | |
| TST | TST<cond> Rn, Rm{, <shift>} | Test bits | CPSR flags set on (Rn & {shifted Rm}) | |
| Branch Instructions | ||||
| B | B<cond> imm | Branch relative | PC = PC + address | |
| BL | BL<cond> imm | Branch and link relative | LR = RET PC = PC + address | |
| Miscellaneous Instructions | ||||
| SWI | SWI<cond> imm | Software interrupt | LR = RET Execute SWI vector in supervisor mode | |
