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{{arm title|ARMv1}}
 
{{arm title|ARMv1}}
'''ARMv1''' is the first [[ARM]] instruction set version. Introduced with the {{armh|ARM1}} on April 26 1985, the ARMv1 defines a {{arch|32}} ISA along with {{arm|26-bit|26-bit addressing space}}.
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'''ARMv1''' is the first [[ARM]] instruction set version. Introduced with the {{armh|ARM1}} on April 26 1985, the ARMv1 defines a {{arch|32}} ISA along with {{arm|26-bit|26-bit addressing space}}. The ARMv1 was only implemented by the {{armh|ARM1}} and was replaced soon after by the {{armh|ARM2}}. Only a few hundred of those chips were ever fabricated.
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 +
== Overview ==
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The ARMv1 is a simple architecture. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a [[program counter]] which is 26 bits in size allowing for an address space of up to 64 MiB of data.
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 +
== Registers ==
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There are 16 [[general purpose registers|general purpose]] 32-bit registers. With the exception of {{arm|R15|register 15}}, all registers are orthogonal with no specific designated purpose.
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 +
== Instruction Listing ==
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The ARMv1 is broken down into 2 classes of instruction:
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* [[#load_instructions|Load Instructions]]
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* [[#store_instructions|Store Instructions]]
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{{isa
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| title    = ARMv1 ISA
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| Syntax
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| Description
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| Action
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| cols = 5
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| listing  =
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{{inst|cols=5|section=<span id="load_instructions">'''Load Instructions'''</span>}}
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{{inst|mn=LDR  |col 1=LDR{cond} Rd, address  |col 2=Load [[Word]]                      |col 3 = Rd = [address]}}
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{{inst|mn=LDRT |col 1=LDRT{cond} Rd, address  |col 2=Load [[Word]], User Mode Privilege |col 3 = Rd = [address]}}
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{{inst|mn=LDRB |col 1=LDRB{cond} Rd, address  |col 2=Load [[Byte]]                      |col 3 = Rd = ZeroExtend([address])}}
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{{inst|mn=LDRBT|col 1=LDRBT{cond} Rd, address |col 2=Load [[Byte]], User Mode Privilege |col 3 = Rd = ZeroExtend([address])}}
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{{inst|mn=LDM  |col 1=LDM{cond}{type} Rn[!], {reglist} |col 2= Load Multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Rd = [addr]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr += {type} }}
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{{inst|mn=LDM  |col 1=LDM{cond}{type} Rn[!], {reglist, PC} |col 2= Load Multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Rd = [addr]<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr += {type}<br>R15 = [addr] }}
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{{inst|cols=5|section=<span id="store_instructions">'''Store Instructions'''</span>}}
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{{inst|mn=STR  |col 1=STR{cond} Rd, address    |col 2=Store Word                      |col 3 = [address] = Rd}}
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{{inst|mn=STRT  |col 1=STRT{cond} Rd, address    |col 2=Store Word, User Mode Privilege  |col 3 = [address] = Rd}}
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{{inst|mn=STRB  |col 1=STRB{cond} Rd, address    |col 2=Store Byte                      |col 3 = [address][7:0] = Rd[7:0]}}
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{{inst|mn=STRBT |col 1=STRBT{cond} Rd, address  |col 2=Store Byte, User Mode Privilege  |col 3 = [address][7:0] = Rd[7:0]}}
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{{inst|mn=STM  |col 1=STM{cond}{type} Rn[!], {reglist} |col 2= Store Multiple |col 3 = addr = Rn<br>for each Rd in {reglist}:<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[addr] = Rd<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;addr += {type} }}
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{{inst|mn=STM  |col 1=STM{cond}{type} Rn[!], {reglist}^ |col 2= Store Multiple, User Mode Privilege |col 3 = addr = Rn<br>for each Rd in {reglist}:<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;[addr]
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= Rd<br>&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;Rn += {type} }}
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}}

Revision as of 23:00, 26 June 2017

ARMv1 is the first ARM instruction set version. Introduced with the ARM1 on April 26 1985, the ARMv1 defines a 32-bit ISA along with 26-bit addressing space. The ARMv1 was only implemented by the ARM1 and was replaced soon after by the ARM2. Only a few hundred of those chips were ever fabricated.

Overview

The ARMv1 is a simple architecture. Each instruction is 32-bit in size and operates on two 32-bit operands. There is a program counter which is 26 bits in size allowing for an address space of up to 64 MiB of data.

Registers

There are 16 general purpose 32-bit registers. With the exception of register 15, all registers are orthogonal with no specific designated purpose.

Instruction Listing

The ARMv1 is broken down into 2 classes of instruction:

ARMv1 ISA
Mnemonic Syntax Description Action
Load Instructions
LDRLDR{cond} Rd, addressLoad WordRd = [address]
LDRTLDRT{cond} Rd, addressLoad Word, User Mode PrivilegeRd = [address]
LDRBLDRB{cond} Rd, addressLoad ByteRd = ZeroExtend([address])
LDRBTLDRBT{cond} Rd, addressLoad Byte, User Mode PrivilegeRd = ZeroExtend([address])
LDMLDM{cond}{type} Rn[!], {reglist}Load Multipleaddr = Rn
for each Rd in {reglist}:
     Rd = [addr]
     addr += {type}
LDMLDM{cond}{type} Rn[!], {reglist, PC}Load Multipleaddr = Rn
for each Rd in {reglist}:
     Rd = [addr]
     addr += {type}
R15 = [addr]
Store Instructions
STRSTR{cond} Rd, addressStore Word[address] = Rd
STRTSTRT{cond} Rd, addressStore Word, User Mode Privilege[address] = Rd
STRBSTRB{cond} Rd, addressStore Byte[address][7:0] = Rd[7:0]
STRBTSTRBT{cond} Rd, addressStore Byte, User Mode Privilege[address][7:0] = Rd[7:0]
STMSTM{cond}{type} Rn[!], {reglist}Store Multipleaddr = Rn
for each Rd in {reglist}:
     [addr] = Rd
     addr += {type}
STMSTM{cond}{type} Rn[!], {reglist}^Store Multiple, User Mode Privilegeaddr = Rn
for each Rd in {reglist}:
     [addr] = Rd
     Rn += {type}