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== MMU == | == MMU == | ||
− | + | Under AArch64, the virtual address space for each TTBR can be up to 48 bits. This is supported at run-time with lower values benefitting from a smaller table walk. The upper 8 bits of the address is ignored for the purpose of address translation, allowing software to use it for tagged pointers. The physical address space was also defined to support up to 48 bits. | |
The supported granule sizes are 4 KiB, 16 KiB, and 64 KiB. This corresponds to the size of the smallest page supported as well as the size of the translation tables in memory. Which of the three supported is up to the implementation. | The supported granule sizes are 4 KiB, 16 KiB, and 64 KiB. This corresponds to the size of the smallest page supported as well as the size of the translation tables in memory. Which of the three supported is up to the implementation. |