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The most major difference is in the [[Program Counter]] which only implements a 24-bit program counter in {{arm|R15}}. This allows for an address space of only up to 64 MiB (note that all instructions are {{arm|Word}}-aligned, therefore the two low bits are always zero; <code>2<sup>24</sup> << 2</code>). Any memory access attempt beyond the <math>2^{26}-1</math> byte will raise a memory access exception. On the {{arm|32-bit architectures}}, the program counter was extended to 30 bits, allowing the full 4 GiB address space to be accessible. Because addresses are only 26 bits there were no restrictions on {{arm|branches}} wrapping around either past ''0x3FFFFFF'' or backwards past 0x0000000. This would lead to 26-bit architectures having different target address than they would on a 32-bit ARM architecture. Consequently, <code>B</code> and <code>BL</code> signed 24-bit offsets can branch to any address.
 
The most major difference is in the [[Program Counter]] which only implements a 24-bit program counter in {{arm|R15}}. This allows for an address space of only up to 64 MiB (note that all instructions are {{arm|Word}}-aligned, therefore the two low bits are always zero; <code>2<sup>24</sup> << 2</code>). Any memory access attempt beyond the <math>2^{26}-1</math> byte will raise a memory access exception. On the {{arm|32-bit architectures}}, the program counter was extended to 30 bits, allowing the full 4 GiB address space to be accessible. Because addresses are only 26 bits there were no restrictions on {{arm|branches}} wrapping around either past ''0x3FFFFFF'' or backwards past 0x0000000. This would lead to 26-bit architectures having different target address than they would on a 32-bit ARM architecture. Consequently, <code>B</code> and <code>BL</code> signed 24-bit offsets can branch to any address.
  
The 26-bit architectures do not have a {{arm|CPSR}} or any {{arm|SPSR}}s. and only the four original modes are supported: <code>User</code>, <code>FIQ</code>, <code>IRQ</code>, and <code>Supervisor</code>. The remaining bits in the program counter are used for the condition flags (N, Z, C, and V), interrupt disable flags (I and F), and the two processor mode bits (M1 and M0). This had the effect of being able to save the process status across subroutine calls and without adding any additional instructions or overhead (e.g. special entry and exit sequence).
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The 26-bit architectures do not have a {{arm|CPSR}} or any {{arm|SPSR}}s. and only the four original modes are supported: <code>User</code>, <code>FIQ</code>, <code>IRQ</code>, and <code>Supervisor</code>. The remaining bits in the program counter are used for the condition flags (N, Z, C, and V), interrupt disable flags (I and F), and the two processor mode bits (M1 and M0). This had the effect of being able to save the process status across subroutine calls and without adding any additional instructions or overhead (e.g. special entry and exit sequence).  
 
 
:<table style="text-align: center;"><tr><td>31</td><td>30</td><td>29</td><td>28</td><td>27</td><td>26</td><td>25</td><td colspan="22">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;</td><td>2</td><td>1</td><td>0</td></tr><tr><td style="border: 1px solid black;">N</td><td style="border: 1px solid black;">Z</td><td style="border: 1px solid black;">C</td><td style="border: 1px solid black;">V</td><td style="border: 1px solid black;">I</td><td style="border: 1px solid black;">F</td><td style="border: 1px solid black;" colspan="24">Program Counter</td><td style="border: 1px solid black;">M1</td><td style="border: 1px solid black;">M0</td></tr></table>
 
 
 
* R15[25:2] = ''Program Counter'' (PC)
 
* R15[31:26], R15[1:0] = ''Program Status Register'' (PSR)
 
  
 
== 26-bit ARM Architectures and implementations ==
 
== 26-bit ARM Architectures and implementations ==

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