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Difference between revisions of "apm/microarchitectures/storm"
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'''Storm''' is [[AppliedMicro]] first custom [[ARM]] microarchitecture for servers. Storm-based microprocessors were sold under the {{apm|X-Gene 1}} brand of server microprocessors.
 
'''Storm''' is [[AppliedMicro]] first custom [[ARM]] microarchitecture for servers. Storm-based microprocessors were sold under the {{apm|X-Gene 1}} brand of server microprocessors.
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== Codenames ==
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{| class="wikitable"
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|-
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! Codename !! Description
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|-
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| Potenza || codename for the core and memory sub-system
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|}
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== Technology ==
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Storm is fabricated on TSMC's [[40 nm]] bluk CMOS.
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== Architecture ==
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=== Memory Hierarchy ===
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* Cache
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** L1I
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*** 32 KiB, 8-way set associative
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**** Per core
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*** ECC and Parity protection
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** L1D
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*** 32 KiB, 8-way set associative
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**** Per core
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*** 64 B/line
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*** Write-through with [[write-combining]]
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*** ECC and Parity protection
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** L2
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*** 256 KB
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**** Per process module (2 cores)
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***  Inclusive of L1 write-thru data caches
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*** 64 B/line
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*** ECC and Parity protection
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** L3
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*** 8 MiB
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*** 64 B/line

Revision as of 20:36, 25 September 2018

Edit Values
Storm µarch
General Info
Arch TypeCPU
DesignerAppliedMicro
ManufacturerTSMC
Introduction2011
Process40 nm
Core Configs8
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Instructions
ISAARMv8
Succession

Storm is AppliedMicro first custom ARM microarchitecture for servers. Storm-based microprocessors were sold under the X-Gene 1 brand of server microprocessors.

Codenames

Codename Description
Potenza codename for the core and memory sub-system

Technology

Storm is fabricated on TSMC's 40 nm bluk CMOS.

Architecture

Memory Hierarchy

  • Cache
    • L1I
      • 32 KiB, 8-way set associative
        • Per core
      • ECC and Parity protection
    • L1D
      • 32 KiB, 8-way set associative
        • Per core
      • 64 B/line
      • Write-through with write-combining
      • ECC and Parity protection
    • L2
      • 256 KB
        • Per process module (2 cores)
      • Inclusive of L1 write-thru data caches
      • 64 B/line
      • ECC and Parity protection
    • L3
      • 8 MiB
      • 64 B/line
codenameStorm +
core count8 +
designerAppliedMicro +
first launched2011 +
full page nameapm/microarchitectures/storm +
instance ofmicroarchitecture +
instruction set architectureARMv8 +
manufacturerTSMC +
microarchitecture typeCPU +
nameStorm +
process40 nm (0.04 μm, 4.0e-5 mm) +