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(Created page with "{{amd title|Ryzen Threadripper 1950X}} {{mpu |name=Ryzen Threadripper 1950X |no image=Yes |image size=250px |designer=AMD |manufacturer=GlobalFoundries |model number=1950X |ma...")
 
("set to be introduced" → "introduced")
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{{amd title|Ryzen Threadripper 1950X}}
 
{{amd title|Ryzen Threadripper 1950X}}
 
{{mpu
 
{{mpu
 +
|future=Yes
 
|name=Ryzen Threadripper 1950X
 
|name=Ryzen Threadripper 1950X
 
|no image=Yes
 
|no image=Yes
|image size=250px
 
 
|designer=AMD
 
|designer=AMD
 
|manufacturer=GlobalFoundries
 
|manufacturer=GlobalFoundries
 
|model number=1950X
 
|model number=1950X
 +
|part number=YD195XA8UGAAE
 
|market=Desktop
 
|market=Desktop
 +
|first announced=July 13, 2017
 +
|first launched=August 10, 2017
 +
|release price=$999
 
|family=Ryzen Threadripper
 
|family=Ryzen Threadripper
 
|series=Ryzen
 
|series=Ryzen
 
|locked=No
 
|locked=No
 
|frequency=3,400 MHz
 
|frequency=3,400 MHz
|turbo frequency1=
+
|turbo frequency1=4,000 MHz
 +
|turbo frequency2=4,000 MHz
 
|bus links=4
 
|bus links=4
 
|bus rate=8 GT/s
 
|bus rate=8 GT/s
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|isa family=x86
 
|isa family=x86
 
|microarch=Zen
 
|microarch=Zen
|chipset=Promontory
+
|chipset=X399
 
|core family=23
 
|core family=23
 
|core model=1
 
|core model=1
|core stepping=2
+
|core stepping=B1
 
|process=14 nm
 
|process=14 nm
 
|transistors=9,600,000,000
 
|transistors=9,600,000,000
 
|technology=CMOS
 
|technology=CMOS
|die area=195.228 mm²
+
|die area=213 mm²
|die length=8.87 mm
 
|die width=22.01 mm
 
 
|mcp=Yes
 
|mcp=Yes
 
|die count=2
 
|die count=2
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|thread count=32
 
|thread count=32
 
|max cpus=1
 
|max cpus=1
|max memory=64 GiB
+
|max memory=1 TiB
|tdp=155 W
+
|tdp=180 W
 
|package module 1={{packages/amd/socket tr4}}
 
|package module 1={{packages/amd/socket tr4}}
|turbo frequency=Yes
 
 
}}
 
}}
 +
'''Ryzen Threadripper 1950X''' is a {{arch|64}} [[hexadeca-core]] high-performance [[x86]] desktop [[microprocessor]] introduced by [[AMD]] in mid-[[2017]]. The 1950X, which is based on their {{amd|Zen|Zen microarchitecture|l=arch}}, is fabricated on a [[14 nm process]]. The 1950X operates at a base frequency of 3.4 GHz with a with a [[TDP]] of 180 W and a {{amd|Precision Boost|Boost}} frequency of 4.0 GHz. This MPU supports up to 1 TiB of quad-channel DDR4-2666 ECC memory.
 +
 +
As with the rest of the {{amd|Threadripper}} family based on {{amd|Zen|l=arch}}, the 1950X consists of all four cores active in each {{amd|Zen#CPU Complex (CCX)|CPU Complex (CCX)|l=arch}} in each die. That is, [[four cores]] in each CCX in each of the dies are active for a total of [[sixteen cores]] in the entire [[package]] (4+4 [Die 1] + 4+4 [Die 2]).
 +
 +
 +
{{unknown features}}
 +
 +
 +
== Cache ==
 +
{{main|amd/microarchitectures/zen#Memory_Hierarchy|l1=Zen § Cache}}
 +
{{cache size
 +
|l1 cache=1.5 MiB
 +
|l1i cache=1 MiB
 +
|l1i break=16x64 KiB
 +
|l1i desc=4-way set associative
 +
|l1d cache=512 KiB
 +
|l1d break=16x32 KiB
 +
|l1d desc=8-way set associative
 +
|l1d policy=write-back
 +
|l2 cache=8 MiB
 +
|l2 break=16x512 KiB
 +
|l2 desc=8-way set associative
 +
|l2 policy=write-back
 +
|l3 cache=32 MiB
 +
|l3 break=4x8 MiB
 +
|l3 desc=16-way set associative
 +
}}
 +
 +
== Memory controller ==
 +
This CPU supports 8 DIMMs of rates 1,333 MT/s - 3,200 MT/s (UDIMM/SODIMM).
 +
{{memory controller
 +
|type=DDR4-2666
 +
|ecc=Yes
 +
|max mem=1 TiB
 +
|controllers=4
 +
|channels=4
 +
|max bandwidth=79.47 GiB/s
 +
|bandwidth schan=19.87 GiB/s
 +
|bandwidth dchan=39.74 GiB/s
 +
|bandwidth qchan=79.47 GiB/s
 +
}}
 +
 +
{{amd ryzen threadripper memory configs}}
 +
 +
== Expansions ==
 +
This processor includes 60 PCIe lanes with PHY of 16 lanes may each have a maximum of 8 PCIe ports (x1, x2, x4, x8, x16).
 +
{{expansions
 +
| pcie revision      = 3.0
 +
| pcie lanes        = 60
 +
| pcie config        = x16
 +
| pcie config 2      = x8
 +
| pcie config 3      = x4
 +
| pcie config 4      = x1
 +
}}
 +
* eMMC, LPC, SMBus, SPI/eSPI
 +
 +
== Graphics ==
 +
This processor has no integrated graphics.
 +
 +
== Features ==
 +
{{x86 features
 +
|real=Yes
 +
|protected=Yes
 +
|smm=Yes
 +
|fpu=Yes
 +
|x8616=Yes
 +
|x8632=Yes
 +
|x8664=Yes
 +
|nx=Yes
 +
|mmx=Yes
 +
|emmx=Yes
 +
|sse=Yes
 +
|sse2=Yes
 +
|sse3=Yes
 +
|ssse3=Yes
 +
|sse41=Yes
 +
|sse42=Yes
 +
|sse4a=Yes
 +
|avx=Yes
 +
|avx2=Yes
 +
 +
|abm=Yes
 +
|tbm=No
 +
|bmi1=Yes
 +
|bmi2=Yes
 +
|fma3=Yes
 +
|fma4=No
 +
|aes=Yes
 +
|rdrand=Yes
 +
|sha=Yes
 +
|xop=No
 +
|adx=Yes
 +
|clmul=Yes
 +
|f16c=Yes
 +
|tbt1=No
 +
|tbt2=No
 +
|tbmt3=No
 +
|bpt=No
 +
|eist=No
 +
|sst=No
 +
|flex=No
 +
|fastmem=No
 +
|isrt=No
 +
|sba=No
 +
|mwt=No
 +
|sipp=No
 +
|att=No
 +
|ipt=No
 +
|tsx=No
 +
|txt=No
 +
|ht=No
 +
|vpro=No
 +
|vtx=No
 +
|vtd=No
 +
|ept=No
 +
|mpx=No
 +
|sgx=No
 +
|securekey=No
 +
|osguard=No
 +
|3dnow=No
 +
|e3dnow=No
 +
|smartmp=No
 +
|powernow=No
 +
|amdvi=Yes
 +
|amdv=Yes
 +
|amdsme=No
 +
|amdsev=No
 +
|rvi=No
 +
|smt=Yes
 +
|sensemi=Yes
 +
|xfr=Yes
 +
}}
 +
 +
* This model has full {{amd|XFR}} support, allowing for an additional +[[amd xfr headroom::200 MHz]] boost frequency.

Revision as of 10:24, 11 November 2017

Template:mpu Ryzen Threadripper 1950X is a 64-bit hexadeca-core high-performance x86 desktop microprocessor introduced by AMD in mid-2017. The 1950X, which is based on their Zen microarchitecture, is fabricated on a 14 nm process. The 1950X operates at a base frequency of 3.4 GHz with a with a TDP of 180 W and a Boost frequency of 4.0 GHz. This MPU supports up to 1 TiB of quad-channel DDR4-2666 ECC memory.

As with the rest of the Threadripper family based on Zen, the 1950X consists of all four cores active in each CPU Complex (CCX) in each die. That is, four cores in each CCX in each of the dies are active for a total of sixteen cores in the entire package (4+4 [Die 1] + 4+4 [Die 2]).


DIL16 Blank.svg Preliminary Data! Information presented in this article deal with a microprocessor or chip that was recently announced or leaked, thus missing information regarding its features and exact specification. Information may be incomplete and can change by final release.


Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$1.5 MiB
1,536 KiB
1,572,864 B
L1I$1 MiB
1,024 KiB
1,048,576 B
16x64 KiB4-way set associative 
L1D$512 KiB
524,288 B
0.5 MiB
16x32 KiB8-way set associativewrite-back

L2$8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
  16x512 KiB8-way set associativewrite-back

L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  4x8 MiB16-way set associative 

Memory controller

This CPU supports 8 DIMMs of rates 1,333 MT/s - 3,200 MT/s (UDIMM/SODIMM).

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-2666
Supports ECCYes
Max Mem1 TiB
Controllers4
Channels4
Max Bandwidth79.47 GiB/s
81,377.28 MiB/s
85.33 GB/s
85,330.263 MB/s
0.0776 TiB/s
0.0853 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
Quad 79.47 GiB/s
[Edit] Official AMD Supported Memory Configurations
Quad Channel Single Rank 1 DIMM per channel 4 of 8 DDR4-2666
2 DIMMs per channel 8 of 8 DDR4-2133
Dual Rank 1 DIMM per channel 4 of 8 DDR4-2400
2 DIMMs per channel 8 of 8 DDR4-1866

Expansions

This processor includes 60 PCIe lanes with PHY of 16 lanes may each have a maximum of 8 PCIe ports (x1, x2, x4, x8, x16).

[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIe
Revision3.0
Max Lanes60
Configsx16, x8, x4, x1
  • eMMC, LPC, SMBus, SPI/eSPI

Graphics

This processor has no integrated graphics.

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SenseMISenseMI Technology
XFRExtended Frequency Range
  • This model has full XFR support, allowing for an additional +200 MHz
    0.2 GHz
    200,000 kHz
    boost frequency.
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Ryzen Threadripper 1950X - AMD#io +
amd xfr headroom200 MHz (0.2 GHz, 200,000 kHz) +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd extended frequency rangetrue +
has amd sensemi technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Extended Frequency Range +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size1,536 KiB (1,572,864 B, 1.5 MiB) +
l1d$ description8-way set associative +
l1d$ size512 KiB (524,288 B, 0.5 MiB) +
l1i$ description4-way set associative +
l1i$ size1,024 KiB (1,048,576 B, 1 MiB) +
l2$ description8-way set associative +
l2$ size8 MiB (8,192 KiB, 8,388,608 B, 0.00781 GiB) +
l3$ description16-way set associative +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
max memory bandwidth79.47 GiB/s (81,377.28 MiB/s, 85.33 GB/s, 85,330.263 MB/s, 0.0776 TiB/s, 0.0853 TB/s) +
max memory channels4 +
max pcie lanes60 +
supported memory typeDDR4-2666 +