From WikiChip
Editing amd/ryzen embedded

Warning: You are not logged in. Your IP address will be publicly visible if you make any edits. If you log in or create an account, your edits will be attributed to your username, along with other benefits.

The edit can be undone. Please check the comparison below to verify that this is what you want to do, and then save the changes below to finish undoing the edit.

This page supports semantic in-text annotations (e.g. "[[Is specified as::World Heritage Site]]") to build structured and queryable content provided by Semantic MediaWiki. For a comprehensive description on how to use annotations or the #ask parser function, please have a look at the getting started, in-text annotation, or inline queries help pages.

Latest revision Your text
Line 87: Line 87:
 
Introduced in early 2019, the R1000 embedded series is based on the {{amd|Zen|Zen microarchitecture|l=arch}}. Those models come in either [[dual-core]] or [[quad-core]] models with [[SMT]] and a {{amd|Vega|l=arch}} integrated graphics processor in {{amd|FP5|package FP5|l=package}}. All models have the following features in common.
 
Introduced in early 2019, the R1000 embedded series is based on the {{amd|Zen|Zen microarchitecture|l=arch}}. Those models come in either [[dual-core]] or [[quad-core]] models with [[SMT]] and a {{amd|Vega|l=arch}} integrated graphics processor in {{amd|FP5|package FP5|l=package}}. All models have the following features in common.
  
* '''Mem:''' Single/dual-channel 64-bit DDR4-2400 w/ ECC, up to 32 GiB
+
* '''Mem:''' Dual-channel 64-bit DDR4-3200 or DDR-2400 w/ ECC, up to 32 GiB
* '''I/O:''' Up to 8 PCIe lanes, up to 2 SATA ports, up to 2 Gigabit Ethernet ports, 6 USB ports (4 USB 3.1 ports, one supporting Type-C connectors with DisplayPort Alternate Mode and PD capability)
+
* '''I/O:''' 8 PCIe lanes, dual 10 Gigabit Ethernet, and four USB 3.1 Gen ports (two of which can be configured as Type-C with DisplayPort Alternate Mode PD). A few of the PCIe lanes can also be reconfigured as SATA ports (up to 2 ports).
* '''TDP:''' 6-15 W (with cTDP-up and cTDP-down options)
+
* '''TDP:'''15 W (with cTDP-up and cTDP-down options)
 
* '''ISA:''' Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}}
 
* '''ISA:''' Everything up to {{x86||AVX2}} (i.e., {{x86|SMM}}, {{x86|FPU}}, {{x86|NX}}, {{x86|MMX}}, {{x86|SSE}}, {{x86|SSE2}}, {{x86|SSE3}}, {{x86|SSSE3}}, {{x86|SSE4.1}}, {{x86|SSE4.2}}, {{x86|AES}}, {{x86|AVX}}, {{x86|FMA3}}, and {{x86|AVX2}}), and {{x86|SHA}}
 
* '''Tech:''' {{amd|Precision Boost}}, 2-way [[SMT]], {{amd|AMD-Vi}}, {{amd|AMD-V}}, {{amd|Secure Memory Encryption}} (SME), and {{amd|Secure Encrypted Virtualization}} (SEV)
 
* '''Tech:''' {{amd|Precision Boost}}, 2-way [[SMT]], {{amd|AMD-Vi}}, {{amd|AMD-V}}, {{amd|Secure Memory Encryption}} (SME), and {{amd|Secure Encrypted Virtualization}} (SEV)
Line 106: Line 106:
 
{{comp table header|main|9:Central Processor|2:Graphics Processor}}
 
{{comp table header|main|9:Central Processor|2:Graphics Processor}}
 
{{comp table header|cols|Launched|Cores|Thread|L2$|L3$|%TDP|%Base|%Turbo (Max)|Memory|Name|Frequency}}
 
{{comp table header|cols|Launched|Cores|Thread|L2$|L3$|%TDP|%Base|%Turbo (Max)|Memory|Name|Frequency}}
{{#ask: [[Category:microprocessor models by amd]][[family::Ryzen Embedded]][[series::R1000]]
+
{{#ask: [[Category:microprocessor models by amd]] [[core name::Banded Kestrel]]
 
  |?full page name
 
  |?full page name
 
  |?model number
 
  |?model number
Line 125: Line 125:
 
  |mainlabel=-
 
  |mainlabel=-
 
}}
 
}}
{{comp table count|ask=[[Category:microprocessor models by amd]][[family::Ryzen Embedded]][[series::R1000]]}}
+
{{comp table count|ask=[[Category:microprocessor models by amd]] [[core name::Banded Kestrel]]}}
 
</table>
 
</table>
 
{{comp table end}}
 
{{comp table end}}

Please note that all contributions to WikiChip may be edited, altered, or removed by other contributors. If you do not want your writing to be edited mercilessly, then do not submit it here.
You are also promising us that you wrote this yourself, or copied it from a public domain or similar free resource (see WikiChip:Copyrights for details). Do not submit copyrighted work without permission!

Cancel | Editing help (opens in new window)
Facts about "Ryzen Embedded - AMD"
designerAMD +
first announcedFebruary 22, 2018 +
first launchedFebruary 22, 2018 +
full page nameamd/ryzen embedded +
instance ofsystem on a chip family +
instruction set architecturex86-64 +
main designerAMD +
manufacturerGlobalFoundries + and TSMC +
microarchitectureZen + and Zen 2 +
nameAMD Ryzen Embedded +
packagePackage FP5 + and Package FP6 +
process14 nm (0.014 μm, 1.4e-5 mm) + and 7 nm (0.007 μm, 7.0e-6 mm) +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +