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Difference between revisions of "amd/ryzen 7/1800x"
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== Memory controller ==
 
== Memory controller ==
This processors supports 2 DDR4 PHYs, each supporting 1 channel of 64-bit data plus [[ECC]] with 2 1,333 MT/s - 3,200 MT/s DIMMs per channel (UDIMM/SODIMM).
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This processors supports 2 DDR4 PHYs, each supporting 1 channel of 64-bit data plus [[ECC]] with 2 DIMMs per channel. DIMMs of rates 1,333 MT/s - 3,200 MT/s are supported (UDIMM/SODIMM).
 
{{memory controller
 
{{memory controller
 
|type=DDR4-3200
 
|type=DDR4-3200

Revision as of 18:08, 1 May 2017

Template:mpu Ryzen 7 1800X is a 64-bit octa-core top-of-the-line performance x86 desktop SoC introduced by AMD in early 2017. The 1800X is AMD's flagship model based on their Zen microarchitecture, fabricated on a 14 nm process. The 1800X operates at a base frequency of 3.6 GHz with a TDP of 95 W and a Boost frequency of 4.0 GHz. This MPU supports up to 64 GiB of dual-channel DDR4-2666 ECC memory.

Overview

Main article: Zen

The Ryzen 7 1800X is AMD's flagship system on chip based on the Zen microarchitecture. The 1800X integrates eight x86 cores and is the first AMD processor to support 2-way simultaneous multithreading. Sporting a base frequency of 3.6 GHz and a Boost frequency of 4.0 GHz, the 1800X is the fastest of the Ryzen processors. The 1800X is a complete SoC integrating a memory controller, along with much of the southbridge on-die. The 1800X includes 16 PCIe lanes for a GPU along with an NVMe controller and an additional 4 PCIe lanes for I/O along with SATA and USB 3.0 links.

Cache

Main article: Zen § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$768 KiB
786,432 B
0.75 MiB
L1I$512 KiB
524,288 B
0.5 MiB
8x64 KiB4-way set associative 
L1D$256 KiB
262,144 B
0.25 MiB
8x32 KiB8-way set associativewrite-back

L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  8x512 KiB8-way set associativewrite-back

L3$16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
  2x8 MiB16-way set associative 

Memory controller

This processors supports 2 DDR4 PHYs, each supporting 1 channel of 64-bit data plus ECC with 2 DIMMs per channel. DIMMs of rates 1,333 MT/s - 3,200 MT/s are supported (UDIMM/SODIMM).

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-3200
Supports ECCYes
Max Mem64 GiB
Controllers2
Channels2
Max Bandwidth39.74 GiB/s
40,693.76 MiB/s
42.671 GB/s
42,670.5 MB/s
0.0388 TiB/s
0.0427 TB/s
Bandwidth
Single 19.87 GiB/s
Double 39.74 GiB/s
[Edit] Memory Configurations
Dual Channel Single Rank 2 DIMMs DDR4-2666
4 DIMMs DDR4-2133
Double Rank 2 DIMMs DDR4-2400
4 DIMMs DDR4-1866

Expansions

This SoC supports up to two 8x16 PCIe controllers supporting Gen1, Gen2, and Gen3. An additional 6 x4 PHYs plus 5 x2 PHYs supporting PCIe, WAFL, xGMI, SATA and Ethernet (See networking below).

[Edit/Modify Expansions Info]

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Expansion Options
PCIe
Revision3.0
Max Lanes20
Configs1x16+1x4, 2x8+1x4
USB
Revision3.0, 2.0
Ports4
Rate5 Gbit/s
UART
Ports4
SATA
Revision3.0
Ports4

GP I/O6 ports
  • eMMC, LPC, SMBus, SPI/eSPI

Networking

PHYs support for up to 4 lanes of 10/100/1000 SGMII, or 10GBASE-KR, or 1000BASE-KX Ethernet operation.

[Edit/Modify Network Info]

ethernet plug icon.svg
Networking
Ethernet
1 GigEYes (Ports: 4)
10GbEYes (Ports: 4)
MII
RGMIIYes (Ports: 4)

Audio

Support Azalia High Definition Audio

Graphics

This processor has no integrated graphics.

Features

[Edit/Modify Supported Features]

Cog-icon-grey.svg
Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
NXNo-eXecute
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SenseMISenseMI Technology
XFRExtended Frequency Range
  • This model has full XFR support, allowing for an additional +100 MHz boost frequency.

Die Shot

See also: Zen § Die Shot
  • 14 nm process
  • 12 metal layers
  • 2,000 meters of signals
  • 4,800,000,000 transistors
  • 22.01 mm x 8.87 mm
  • ~195.228 mm²

amd zen octa-core die shot.png

Facts about "Ryzen 7 1800X - AMD"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Ryzen 7 1800X - AMD#io +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd extended frequency rangetrue +
has amd sensemi technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Extended Frequency Range +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
l1$ size768 KiB (786,432 B, 0.75 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description4-way set associative +
l1i$ size512 KiB (524,288 B, 0.5 MiB) +
l2$ description8-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ description16-way set associative +
l3$ size16 MiB (16,384 KiB, 16,777,216 B, 0.0156 GiB) +
max memory bandwidth39.74 GiB/s (40,693.76 MiB/s, 42.671 GB/s, 42,670.5 MB/s, 0.0388 TiB/s, 0.0427 TB/s) +
max memory channels2 +
max pcie lanes20 +
supported memory typeDDR4-3200 +