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|designer=AMD | |designer=AMD | ||
|market=Mobile | |market=Mobile | ||
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|first launched=January 4, 2011 | |first launched=January 4, 2011 | ||
|microarch=Bobcat | |microarch=Bobcat | ||
|tdp=18 W | |tdp=18 W | ||
|package name=FT1 | |package name=FT1 | ||
− | + | |package type=Organic Micro Ball Grid Array | |
− | |package type= | ||
|package contacts=413 | |package contacts=413 | ||
|package dimension=19.0 mm | |package dimension=19.0 mm | ||
|package dimension 2=19.0 mm | |package dimension 2=19.0 mm | ||
− | + | |package pitch=0.8-1.0 mm | |
− | |package pitch=0.8 mm | ||
}} | }} | ||
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− | Package FT1 was used in AMD's "Brazos" platform for ultrathin notebooks. All processors in the FT1 package are members of AMD's | + | '''FT1''' was a BGA-413 package for low power [[AMD]] microprocessors with integrated graphics targeting the thin client, embedded and tablet market, the successor to the {{\\|ASB2}} package. Its counterparts for the mainstream mobile and desktop markets are {{\\|Socket FS1}} and {{\\|Socket FM1}}, respectively. FT1 was superseded by the {{\\|FT3}} package. |
+ | |||
+ | Package FT1 was used in AMD's "Brazos" platform for ultrathin notebooks. All processors in the FT1 package are members of AMD's Family 14h with CPU cores based on the {{amd|Bobcat|l=arch}} microarchitecture, and were manufactured on a 40 nm SOI process. | ||
+ | |||
=== Features === | === Features === | ||
− | * | + | * 413-pin lidless micro ball grid array package, 0.8-1.0 mm multi-pitch, 19 × 19 mm, organic substrate |
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− | * | + | * 64 bit DDR3 SDRAM interface up to 667 MHz, PC3-10600 (DDR3-1333), 10.7 GB/s |
− | + | ** Up to 2 UDIMMs or SODIMMs, no ECC support | |
− | ** Up to 2 | ||
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− | * PCIe Gen 1 | + | * PCIe Gen 1.0 and 2.0 (5 GT/s) |
** Configurable x4 General Purpose Ports (4x1, 2x2, 1x2 + 2x1, 1x4) | ** Configurable x4 General Purpose Ports (4x1, 2x2, 1x2 + 2x1, 1x4) | ||
− | ** x4 Unified Media Interface to | + | ** x4 Unified Media Interface to FCH |
* Two independent display controllers | * Two independent display controllers | ||
− | ** 2 × DisplayPort 1.1a | + | ** Up to 2 × DisplayPort/eDP 1.1a up to 2560 × 1600 at 60 Hz, 30 bpp |
− | ** | + | ** 2 × Single link DVI up to 1920 × 1200 at 60 Hz, 24 bpp |
− | ** 1 × | + | ** 1 × Single link LVDS up to 1440 × 900 or 1400 × 1050 at 60 Hz, 18 bpp |
− | ** 1 × | + | ** 1 × HDMI up to 1920 × 1080 at 60 Hz, 36 bpp |
− | + | ** 1 × VGA/DAC | |
− | ** 1 × | + | ** 1 × DVO |
== Chipsets == | == Chipsets == | ||
− | * AMD | + | * AMD FCH A50M/A55E, codename "Hudson" |
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== Processors using package FT1 == | == Processors using package FT1 == | ||
<!-- AMD-47534-3.18; CPUID 00500F10h (ON-B0), 00500F20h (ON-C0) --> | <!-- AMD-47534-3.18; CPUID 00500F10h (ON-B0), 00500F20h (ON-C0) --> | ||
− | * AMD C-Series "Ontario" | + | * AMD C-Series codename "Ontario" |
− | * AMD E-Series "Zacate" | + | * AMD E-Series "Zacate" |
− | * AMD | + | * AMD G-Series |
− | * AMD Z-Series "Desna" | + | * AMD Z-Series "Desna" |
<!-- NOTE: | <!-- NOTE: | ||
− | This table is generated automatically from the data in the actual articles. | + | This table is generated automatically from the data in the actual articles. |
− | If a microprocessor is missing from the list, an appropriate article for it needs to be | + | If a microprocessor is missing from the list, an appropriate article for it needs to be |
− | created and tagged accordingly. | + | created and tagged accordingly. |
− | Missing a chip? please dump its name here: | + | |
+ | Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips | ||
--> | --> | ||
{{comp table start}} | {{comp table start}} | ||
− | <table class="comptable sortable"> | + | <table class="comptable sortable tc13 tc14 tc15 tc16 tc17 tc18 tc19"> |
− | + | <tr class="comptable-header"><th> </th><th colspan="19">List of all FT1-based Processors</th></tr> | |
− | {{comp table header|cols | + | {{comp table header 1|cols=Price, Process, Launched, µarch, Family, Core, C, T, Freq, Turbo, TDP}} |
− | {{#ask: [[Category:microprocessor models by amd]] [[package::FT1]] | + | {{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[package::FT1]] |
− | |?full page name | + | |?full page name |
− | |?model number | + | |?model number |
− | |?family | + | |?release price |
− | |?core count | + | |?process |
− | |? | + | |?first launched |
− | |?base frequency# | + | |?microarchitecture |
− | |? | + | |?microprocessor family |
− | + | |?core name | |
− | |?tdp | + | |?core count |
− | + | |?thread count | |
− | + | |?base frequency#GHz | |
− | |format=template | + | |?turbo frequency (1 core)#GHz |
− | |template=proc table 3 | + | |?tdp |
− | |userparam= | + | |format=template |
− | |mainlabel=- | + | |template=proc table 3 |
+ | |userparam=13 | ||
+ | |mainlabel=- | ||
}} | }} | ||
− | {{comp table count|ask=[[Category:microprocessor models by amd]] [[package::FT1]]}} | + | {{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[package::FT1]]}} |
</table> | </table> | ||
{{comp table end}} | {{comp table end}} | ||
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:[[File:BGA-413 pn.svg|800px]] | :[[File:BGA-413 pn.svg|800px]] | ||
− | + | BGA-413 package ball numbers. | |
== Pin Map == | == Pin Map == | ||
:[[File:BGA-413 pinmap.svg|800px]] | :[[File:BGA-413 pinmap.svg|800px]] | ||
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=== Pin Description === | === Pin Description === | ||
− | {| class="wikitable | + | {| class="wikitable" |
− | !Signal | + | !Signal!!Description |
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|- | |- | ||
− | | | + | |ALERT_L||Programmable pin that can indicate different events, including a SB-TSI interrupt |
|- | |- | ||
− | | | + | |CLKIN_H/L||100 MHz PLL Differential Reference Clock |
|- | |- | ||
− | | | + | |DAC_BLUE, DAC_BLUEB||Blue for Video Monitor Output |
|- | |- | ||
− | | | + | |DAC_GREEN, DAC_GREENB||Green for Video Monitor Output |
|- | |- | ||
− | | | + | |DAC_HSYNC, DAC_VSYNC||Display Horizontal, Vertical Sync |
|- | |- | ||
− | | | + | |DAC_RED, DAC_REDB||Red for Video Monitor Output |
|- | |- | ||
− | | | + | |DAC_SCL, DAC_SDA||I2C Clock, Data for Display (to video monitor) |
|- | |- | ||
− | | | + | |DAC_ZVSS||Compensation Resistor to DAC Ground Pin |
|- | |- | ||
− | | | + | |DBREQ_L/DBRDY||Debug Request/Ready |
|- | |- | ||
− | | | + | |DISP_CLKIN_H/L||100 MHz Display Controller Reference Clock |
|- | |- | ||
− | | | + | |DMAACTIVE_L||Indicated System DMA Activity |
|- | |- | ||
− | | | + | |DP_BLON||Display Panel Backlight Enable |
|- | |- | ||
− | | | + | |DP_DIGON||Display Panel Power Enable |
|- | |- | ||
− | | | + | |DP_VARY_BL||Display Backlight Brightness Control |
|- | |- | ||
− | | | + | |DP_ZVSS||Compensation Resistor to VSS |
|- | |- | ||
− | |LTDP0/TDP1_AUXP/ | + | |LTDP0/TDP1_AUXP/N||DisplayPort Auxiliary Channel |
|- | |- | ||
− | |LTDP0/TDP1_HPD | + | |LTDP0/TDP1_HPD||DisplayPort Hot Plug Detect |
|- | |- | ||
− | | | + | |LTDP0/TDP1_TXP/N[3:0]||DisplayPort Differential Transmitter |
|- | |- | ||
− | | | + | |M0_CS_L[1:0], M1_CS_L[1:0]||DRAM Chip Selects |
|- | |- | ||
− | | | + | |M0_ODT[1:0], M1_ODT[1:0]||DRAM Enable Pin for On Die Termination |
|- | |- | ||
− | | | + | |M_ADD[15:0]||DRAM Column/Row Address |
|- | |- | ||
− | | | + | |M_BANK[2:0]||DRAM Bank Address |
|- | |- | ||
− | | | + | |M_CAS_L||DRAM Column Address Strobe |
|- | |- | ||
− | | | + | |M_CKE[1:0]||DRAM Clock Enable |
|- | |- | ||
− | | | + | |M_CLK_H/L[3:0]||DRAM Differential Clock |
|- | |- | ||
− | | | + | |M_DATA[63:0]||DRAM Interface Data Bus |
|- | |- | ||
− | | | + | |M_DM[7:0]||DRAM Data Mask |
|- | |- | ||
− | | | + | |M_DQS_H/L[7:0]||DRAM Differential Data Strobe |
|- | |- | ||
− | | | + | |M_EVENT_L||DRAM Thermal Event |
|- | |- | ||
− | | | + | |M_RAS_L||DRAM Row Address Strobe |
|- | |- | ||
− | | | + | |M_RESET_L||DRAM Reset Pin for Suspend-to-RAM Power Management Mode |
|- | |- | ||
− | | | + | |M_VREF||Memory Interface Voltage Reference |
|- | |- | ||
− | | | + | |M_WE_L||DRAM Write Enable |
|- | |- | ||
− | | | + | |M_ZVDDIO_MEM_S||Compensation Resistor to VDDIO |
|- | |- | ||
− | |PROCHOT_L | + | |PROCHOT_L||Processor in HTC-active state input/output |
|- | |- | ||
− | | | + | |PWROK||Voltages and CLKIN have reached specified operation |
|- | |- | ||
− | | | + | |P_GPP_TX/RXP/N[3:0]||General Purpose External PCIe Transmit/Receive Data Differential Pairs |
|- | |- | ||
− | | | + | |P_UMI_TX/RXP/N[3:0]||Unified Media Interface Transmit/Receive Data Differential Pairs |
|- | |- | ||
− | | | + | |P_ZVDD_10||Compensation Resistor to P_VDD_10 Power Supply |
|- | |- | ||
− | | | + | |P_ZVSS||Compensation Resistor to VSS |
|- | |- | ||
− | | | + | |RESET_L||Processor Reset |
|- | |- | ||
− | | | + | |RSVD||Reserved |
|- | |- | ||
− | | | + | |SIC, SID||Sideband Temperature Sensor Interface Clock, Data |
|- | |- | ||
− | | | + | |SVC, SVD||Serial VID Interface Clock, Data |
|- | |- | ||
− | |TRST_L | + | |TCK, TDI, TDO, TMS, TRST_L||JTAG interface |
|- | |- | ||
− | |TEST* | + | |TEST*||Test signal |
|- | |- | ||
− | | | + | |THERMTRIP_L||Thermal Sensor Trip output |
|- | |- | ||
− | | | + | |VDDCR_CPU_SENSE||VDDCR_CPU Voltage Monitor Pin |
|- | |- | ||
− | |VDDCR_CPU | + | |VDDCR_CPU||Core Power Supply |
|- | |- | ||
− | | | + | |VDDCR_NB_SENSE||VDDCR_NB Voltage Monitor Pin |
|- | |- | ||
− | |VDDCR_NB | + | |VDDCR_NB||Northbridge Power Supply |
|- | |- | ||
− | | | + | |VDDIO_MEM_S_SENSE||VDDIO_MEM_S Voltage Monitor Pin |
|- | |- | ||
− | |VDDIO_MEM_S|| | + | |VDDIO_MEM_S||DDR SDRAM I/O Ring Power Supply |
|- | |- | ||
− | | | + | |VDDPL_10||1.05 V Supply Pin for System PLL |
|- | |- | ||
− | |VDD_10 | + | |VDD_10||1.05 V Supply Pins |
|- | |- | ||
− | + | |VDD_18_DAC||1.8 V Supply Pin for DAC | |
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− | |VDD_18_DAC | ||
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|- | |- | ||
− | | | + | |VDD_18||1.8 V Supply Pins |
|- | |- | ||
− | | | + | |VDD_33||3.3 V Supply Pin |
|- | |- | ||
− | | | + | |VSSBG_DAC||DAC Ground |
|- | |- | ||
− | | | + | |VSS_SENSE||VSS Voltage Monitor Pin |
|- | |- | ||
− | | | + | |VSS||Ground |
|} | |} | ||
− | == | + | == References == |
− | * | + | * "FT1 Processor Functional Data Sheet", AMD Publ. #44444, Rev. 2.05, November 2010 |
− | * | + | * "BIOS and Kernel Developer’s Guide (BKDG) for AMD Family 14h Models 00h-0Fh Processors", AMD Publ. #43170, Rev. 3.13, February 17, 2012 |
− | * | + | * "Revision Guide for AMD Family 14h Models 00h-0Fh Processors", AMD Publ. #47534, Rev. 3.18, February 26, 2013 |
== See also == | == See also == |
Facts about "Package FT1 - AMD"
designer | AMD + |
first launched | January 4, 2011 + |
instance of | package + |
market segment | Mobile + and Embedded + |
microarchitecture | Bobcat + |
name | FT1 + |
package | FT1 + and UOB413 + |
package contacts | 413 + |
package height | 1.92 mm (0.0756 in) + |
package length | 19 mm (1.9 cm, 0.748 in) + |
package pitch | 0.8 mm (0.0315 in) + |
package type | FC-OBGA + |
package width | 19 mm (1.9 cm, 0.748 in) + |
tdp | 18 W (18,000 mW, 0.0241 hp, 0.018 kW) + |