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Difference between revisions of "amd/microarchitectures/zen 3"
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(added milan core count as confirmed in AMD HPC AI presentation)
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|designer=AMD
 
|designer=AMD
 
|manufacturer=TSMC
 
|manufacturer=TSMC
|introduction=2020
+
|manufacturer 2=GlobalFoundries
|process=7 nm+
+
|introduction=October 8, 2020
 +
|process=7nm
 +
|process 2=12 nm
 +
|type=Superscalar
 +
|oooe=Yes
 +
|speculative=Yes
 +
|renaming=Yes
 +
|stages=19
 +
|decode=4-way
 +
|isa=x86-64
 +
|extension=MOVBE
 +
|extension 2=MMX
 +
|extension 3=SSE
 +
|extension 4=SSE2
 +
|extension 5=SSE3
 +
|extension 6=SSSE3
 +
|extension 7=SSE4A
 +
|extension 8=SSE4.1
 +
|extension 9=SSE4.2
 +
|extension 10=POPCNT
 +
|extension 11=AVX
 +
|extension 12=AVX2
 +
|extension 13=AES
 +
|extension 14=PCLMUL
 +
|extension 15=FSGSBASE
 +
|extension 16=RDRND
 +
|extension 17=FMA3
 +
|extension 18=F16C
 +
|extension 19=BMI
 +
|extension 20=BMI2
 +
|extension 21=RDSEED
 +
|extension 22=ADCX
 +
|extension 23=PREFETCHW
 +
|extension 24=CLFLUSHOPT
 +
|extension 25=XSAVE
 +
|extension 26=SHA
 +
|extension 27=UMIP
 +
|extension 28=CLZERO
 
|predecessor=Zen 2
 
|predecessor=Zen 2
 
|predecessor link=amd/microarchitectures/zen 2
 
|predecessor link=amd/microarchitectures/zen 2
 
|successor=Zen 4
 
|successor=Zen 4
 
|successor link=amd/microarchitectures/zen 4
 
|successor link=amd/microarchitectures/zen 4
|succession=Yes
 
 
}}
 
}}
'''Zen 3''' is a planned [[microarchitecture]] being developed by [[AMD]] as a successor to {{\\|Zen 2}}.
+
'''Zen 3''' is a [[microarchitecture]] being developed by [[AMD]] as a successor to {{\\|Zen 2}}.
  
 
== History ==
 
== History ==
Line 31: Line 67:
 
| {{amd|Genesis Peak|l=core}} || ?/? || Workstation & enthusiasts market processors
 
| {{amd|Genesis Peak|l=core}} || ?/? || Workstation & enthusiasts market processors
 
|-
 
|-
| {{amd|Vermeer|l=core}} || ?/? || Mainstream to high-end desktops & enthusiasts market processors
+
| {{amd|Vermeer|l=core}} || 16/32 || Mainstream to high-end desktops & enthusiasts market processors
 
|-
 
|-
 
| {{amd|Cezanne|l=core}} || ?/? || Mainstream desktop & mobile processors with GPU  
 
| {{amd|Cezanne|l=core}} || ?/? || Mainstream desktop & mobile processors with GPU  
Line 40: Line 76:
  
 
== Architecture ==
 
== Architecture ==
Nothing is currently known about the architectural improvements that are being done for Zen 3.
+
 
 +
There is very limited information available about the architectural improvements of Zen 3.
  
 
=== Key changes from {{\\|Zen 2}} ===
 
=== Key changes from {{\\|Zen 2}} ===
* [[7_nm_lithography_process#N7.2B|7 nm+ process]] (from [[7 nm]]) , 20% more density and 10% power reduction compared to Zen 2.  EUV (Extreme Ultraviolet) lithography 7nm+.
 
  
 +
* +19% IPC
 +
* Unified 8-core CCX with 32 MiB L3$ available to all 8 cores equally. Latency increased by roughly 7 cycles (18%) to an average of 46 cycles.
 +
* Integer unit:
 +
** Integer physical register file increased from 180 to 192 entries
 +
** Issue increased from 7 (existing 4 ALU and 3 AGU) to 10 with 1 new dedicated branch execution port and 2 separated store data pathways.
 +
** Schedulers shared between pairs of ALU + AGU/branch ports instead of dedicated for each.
 +
** Instruction redundancy increased between ports for reduced bottlenecking on a wider variety of instruction streams.
 +
** 8/16/32/64 bit signed integer division/modulo latency improved from 17/22/30/46 cycles to 10/12/14/20. (Unsigned operations are ~1 cycle faster for some of both old/new cases.) Throughput improves proportionately.
 +
* Floating point unit:
 +
** FMA latency reduced by 1 cycle from 5 to 4.
 +
** Fourth and fifth dedicated execution ports added for floating point store and FP-to-int transfer, no longer sharing 2nd FADD port.
 +
** Unified scheduler split into 1 scheduler per FMA/FADD/transfer port set.
 +
** 256b VAES and VPCLMULDQ support for doubled AES and AES-GCM cryptographic throughout.
 +
** Hardware implementation of BMI2 PDEP/PEXT bit scatter/gather operations, compared to prior microcode emulation.
 +
* Load/store:
 +
** Load throughput increased from 2 to 3, if not 256b.
 +
** Store throughput increased from 1 to 2, if not 256b.
 +
** Store queue increase from 48 to 64 slots.
 +
** Page table walkers tripled from 2 to 6 for TLB miss handling.
 +
* Improved prefetching
 +
* Increased branch prediction bandwidth
 +
** "zero-bubble" branch prediction
 +
** L1 BTB doubled from 512 to 1024 entries
 +
* Improved µop cache
 
{{expand list}}
 
{{expand list}}
  
== References ==
+
== All Zen 3 Chips ==
 +
 
 +
<!-- NOTE:
 +
          This table is generated automatically from the data in the actual articles.
 +
          If a microprocessor is missing from the list, an appropriate article for it needs to be
 +
          created and tagged accordingly.
 +
 
 +
          Missing a chip? please dump its name here: http://en.wikichip.org/wiki/WikiChip:wanted_chips
 +
-->
 +
{{comp table start}}
 +
<table class="comptable sortable tc13 tc14 tc15 tc16 tc17 tc18 tc19">
 +
{{comp table header|main|20:List of all Zen 3-based Processors}}
 +
{{comp table header|main|12:Processor|4:Features}}
 +
{{comp table header|cols|Price|Process|Launched|Family|Core|C|T|TDP|L3|Base|Turbo|Max Mem|SMT|SEV|SME|TSME}}
 +
{{comp table header|lsep|25:[[Uniprocessors]]}}
 +
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 3]] [[max cpu count::1]]
 +
|?full page name
 +
|?model number
 +
|?release price
 +
|?process
 +
|?first launched
 +
|?microprocessor family
 +
|?core name
 +
|?core count
 +
|?thread count
 +
|?tdp
 +
|?l3$ size
 +
|?base frequency#GHz
 +
|?turbo frequency#GHz
 +
|?max memory#GiB
 +
|?has simultaneous multithreading
 +
|?has amd secure encrypted virtualization technology
 +
|?has amd secure memory encryption technology
 +
|?has amd transparent secure memory encryption technology
 +
|format=template
 +
|template=proc table 3
 +
|userparam=18:15
 +
|mainlabel=-
 +
|valuesep=,
 +
|limit=100
 +
}}
 +
{{comp table header|lsep|25:[[Multiprocessors]] (dual-socket)}}
 +
{{#ask: [[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 3]] [[max cpu count::>>1]]
 +
|?full page name
 +
|?model number
 +
|?release price
 +
|?process
 +
|?first launched
 +
|?microprocessor family
 +
|?core name
 +
|?core count
 +
|?thread count
 +
|?tdp
 +
|?l3$ size
 +
|?base frequency#GHz
 +
|?turbo frequency#GHz
 +
|?max memory#GiB
 +
|?has simultaneous multithreading
 +
|?has amd secure encrypted virtualization technology
 +
|?has amd secure memory encryption technology
 +
|?has amd transparent secure memory encryption technology
 +
|format=template
 +
|template=proc table 3
 +
|userparam=18:15
 +
|mainlabel=-
 +
|valuesep=,
 +
|limit=100
 +
}}
 +
{{comp table count|ask=[[Category:microprocessor models by amd]] [[instance of::microprocessor]] [[microarchitecture::Zen 3]]}}
 +
</table>
 +
{{comp table end}}
 +
 
 +
== Designers ==
 +
* Mark Evers, Chief Architect
 +
 
 +
== Bibliography ==
 
* AMD 'Tech Day', February 22, 2017
 
* AMD 'Tech Day', February 22, 2017
 
* AMD 2017 Financial Analyst Day, May 16, 2017
 
* AMD 2017 Financial Analyst Day, May 16, 2017
Line 54: Line 189:
 
* AMD {{\\|Zen}}
 
* AMD {{\\|Zen}}
 
* Intel {{intel|Tigerlake|l=arch}}
 
* Intel {{intel|Tigerlake|l=arch}}
 +
* Read also: [https://www.anandtech.com/print/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested AMD Zen 3 Ryzen Deep Dive Review]

Revision as of 09:09, 19 November 2020

Edit Values
Zen 3 µarch
General Info
Arch TypeCPU
DesignerAMD
ManufacturerTSMC, GlobalFoundries
IntroductionOctober 8, 2020
Process7nm, 12 nm
Pipeline
TypeSuperscalar
OoOEYes
SpeculativeYes
Reg RenamingYes
Stages19
Decode4-way
Instructions
ISAx86-64
ExtensionsMOVBE, MMX, SSE, SSE2, SSE3, SSSE3, SSE4A, SSE4.1, SSE4.2, POPCNT, AVX, AVX2, AES, PCLMUL, FSGSBASE, RDRND, FMA3, F16C, BMI, BMI2, RDSEED, ADCX, PREFETCHW, CLFLUSHOPT, XSAVE, SHA, UMIP, CLZERO
Succession

Zen 3 is a microarchitecture being developed by AMD as a successor to Zen 2.

History

amd zen future roadmap.jpg

Zen 3 was formally disclosed in a roadmap by Lisa Su, AMD's CEO, during AMD's Tech Day in February of 2017. Zen 3 will be the 3rd iteration of the Zen microarchitecture. On Investor's Day in May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 3 is set to utilize 7nm+ process.

Codenames

amd zen2-3 roadmap.png
Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Core C/T Target
Milan 64/128 High-end server multiprocessors
Genesis Peak  ?/? Workstation & enthusiasts market processors
Vermeer 16/32 Mainstream to high-end desktops & enthusiasts market processors
Cezanne  ?/? Mainstream desktop & mobile processors with GPU

Process technology

Zen 3 will be fabricated on TSMC's 7nm+ process.

Architecture

There is very limited information available about the architectural improvements of Zen 3.

Key changes from Zen 2

  • +19% IPC
  • Unified 8-core CCX with 32 MiB L3$ available to all 8 cores equally. Latency increased by roughly 7 cycles (18%) to an average of 46 cycles.
  • Integer unit:
    • Integer physical register file increased from 180 to 192 entries
    • Issue increased from 7 (existing 4 ALU and 3 AGU) to 10 with 1 new dedicated branch execution port and 2 separated store data pathways.
    • Schedulers shared between pairs of ALU + AGU/branch ports instead of dedicated for each.
    • Instruction redundancy increased between ports for reduced bottlenecking on a wider variety of instruction streams.
    • 8/16/32/64 bit signed integer division/modulo latency improved from 17/22/30/46 cycles to 10/12/14/20. (Unsigned operations are ~1 cycle faster for some of both old/new cases.) Throughput improves proportionately.
  • Floating point unit:
    • FMA latency reduced by 1 cycle from 5 to 4.
    • Fourth and fifth dedicated execution ports added for floating point store and FP-to-int transfer, no longer sharing 2nd FADD port.
    • Unified scheduler split into 1 scheduler per FMA/FADD/transfer port set.
    • 256b VAES and VPCLMULDQ support for doubled AES and AES-GCM cryptographic throughout.
    • Hardware implementation of BMI2 PDEP/PEXT bit scatter/gather operations, compared to prior microcode emulation.
  • Load/store:
    • Load throughput increased from 2 to 3, if not 256b.
    • Store throughput increased from 1 to 2, if not 256b.
    • Store queue increase from 48 to 64 slots.
    • Page table walkers tripled from 2 to 6 for TLB miss handling.
  • Improved prefetching
  • Increased branch prediction bandwidth
    • "zero-bubble" branch prediction
    • L1 BTB doubled from 512 to 1024 entries
  • Improved µop cache

This list is incomplete; you can help by expanding it.

All Zen 3 Chips

 List of all Zen 3-based Processors
 ProcessorFeatures
ModelPriceProcessLaunchedFamilyCoreCTTDPL3BaseTurboMax MemSMTSEVSMETSME
 Uniprocessors
Ryzen 5 5600X$ 299.00
€ 269.10
£ 242.19
¥ 30,895.67
7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
5 November 2020Ryzen 5Vermeer61265 W
65,000 mW
0.0872 hp
0.065 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.7 GHz
3,700 MHz
3,700,000 kHz
4.6 GHz
4,600 MHz
4,600,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
Ryzen 7 5800X$ 449.00
€ 404.10
£ 363.69
¥ 46,395.17
7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
5 November 2020Ryzen 7Vermeer816105 W
105,000 mW
0.141 hp
0.105 kW
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
3.8 GHz
3,800 MHz
3,800,000 kHz
4.7 GHz
4,700 MHz
4,700,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
Ryzen 9 5900X$ 549.00
€ 494.10
£ 444.69
¥ 56,728.17
7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
5 November 2020Ryzen 9Vermeer1224105 W
105,000 mW
0.141 hp
0.105 kW
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
3.7 GHz
3,700 MHz
3,700,000 kHz
4.8 GHz
4,800 MHz
4,800,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
Ryzen 9 5950X$ 799.00
€ 719.10
£ 647.19
¥ 82,560.67
7 nm
0.007 μm
7.0e-6 mm
, 12 nm
0.012 μm
1.2e-5 mm
5 November 2020Ryzen 9Vermeer1632105 W
105,000 mW
0.141 hp
0.105 kW
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
3.4 GHz
3,400 MHz
3,400,000 kHz
4.9 GHz
4,900 MHz
4,900,000 kHz
128 GiB
131,072 MiB
134,217,728 KiB
137,438,953,472 B
0.125 TiB
 Multiprocessors (dual-socket)
Count: 4

Designers

  • Mark Evers, Chief Architect

Bibliography

  • AMD 'Tech Day', February 22, 2017
  • AMD 2017 Financial Analyst Day, May 16, 2017

See Also

codenameZen 3 +
designerAMD +
first launchedOctober 8, 2020 +
full page nameamd/microarchitectures/zen 3 +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerTSMC + and GlobalFoundries +
microarchitecture typeCPU +
nameZen 3 +
pipeline stages19 +
process7 nm (0.007 μm, 7.0e-6 mm) + and 12 nm (0.012 μm, 1.2e-5 mm) +