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{| class="wikitable"
 
{| class="wikitable"
 
|-
 
|-
! Processor Series !! Cores/Threads !! Market
+
! Product Line !! Cores/Threads !! Target
 
|-
 
|-
 
| EPYC 7003 "{{amd|Milan|l=core}}" || Up to 64/128 || High-end server [[multiprocessors]]
 
| EPYC 7003 "{{amd|Milan|l=core}}" || Up to 64/128 || High-end server [[multiprocessors]]
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| {{amd|Trento|l=core}}<!--s/a Milan page--> || ?/? || High-performance computing
 
| {{amd|Trento|l=core}}<!--s/a Milan page--> || ?/? || High-performance computing
 
|-
 
|-
| Ryzen Threadripper 5900 "{{amd|Chagall|l=core}}" || Up to 64/128 || Workstation processors
+
| {{amd|Genesis Peak|l=core}} || ?/? || Workstation & enthusiasts market processors
 
|-
 
|-
 
| Ryzen 5000 "{{amd|Vermeer|l=core}}" || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors
 
| Ryzen 5000 "{{amd|Vermeer|l=core}}" || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors
 
|-
 
|-
| Ryzen 5000 APU "{{amd|Cezanne|l=core}}" || Up to 8/16 || Mainstream desktop & mobile processors with integrated GPU
+
| Ryzen 5000 APU "{{amd|Cezanne|l=core}}" || Up to 8/16 || Mainstream desktop & mobile processors with GPU
 
|}
 
|}
  
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== Architecture ==
 
== Architecture ==
 +
 +
There is very limited information available about the architectural improvements of Zen 3.
  
 
=== Key changes from {{\\|Zen 2}} ===
 
=== Key changes from {{\\|Zen 2}} ===
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* {{x86|SME|SEV-SNP}} - 3rd generation Secure Encrypted Virtualization - Secure Nested Paging
 
* {{x86|SME|SEV-SNP}} - 3rd generation Secure Encrypted Virtualization - Secure Nested Paging
 
** <code>PSMASH</code>, <code>PVALIDATE</code>, <code>RMPADJUST</code>, <code>RMPUPDATE</code>
 
** <code>PSMASH</code>, <code>PVALIDATE</code>, <code>RMPADJUST</code>, <code>RMPUPDATE</code>
* {{x86|PSFD}} - Predictive Store Forwarding Disable (Speculation Control MSR)<ref name="amd-psf"/>
+
* {{x86|PSFD}} - Predictive Store Forwarding Disable (Speculation Control MSR)<ref name="amd-psf">[https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf "Security Analysis of AMD Predictive Store Forwarding"], March 2021</ref>
  
Sources: <ref name="amd-24593-apm2"/><ref name="amd-24594-apm3"/><ref name="amd-26568-apm4"/>
+
Sources:<ref name="amd-24593-apm2">{{cite techdoc|title=AMD64 Architecture Programmer's Manual Volume 2: System Programming|url=https://www.amd.com/system/files/TechDocs/24593.pdf|publ=AMD|pid=24593|rev=3.37|date=2021-03}}</ref><ref name="amd-24594-apm3">{{cite techdoc|title=AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and System Instructions|url=https://www.amd.com/system/files/TechDocs/24594.pdf|publ=AMD|pid=24594|rev=3.32|date=2021-03}}</ref><ref name="amd-26568-apm4">{{cite techdoc|title=AMD64 Architecture Programmer's Manual Volume 4: 128-Bit and 256-Bit Media Instructions|url=https://www.amd.com/system/files/TechDocs/26568.pdf|publ=AMD|pid=26568|rev=3.24|date=2020-05}}</ref>
  
 
=== Memory Hierarchy ===
 
=== Memory Hierarchy ===
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** Inclusive of L1
 
** Inclusive of L1
 
** ≥ 12 cycles latency
 
** ≥ 12 cycles latency
** {{abbr|DEC-TED}} ECC, tag & state arrays {{abbr|SEC-DED}}<!--7 check bits for 42 tag bits; AMD-55898-0.50 Sec 3.5-->
+
** ECC
 
* L3 Cache:
 
* L3 Cache:
** "{{amd|Milan|l=core}}" & "{{amd|Chagall|l=core}}": 32 MiB/CCX, up to 256 MiB total
+
** "{{amd|Milan|l=core}}": 32 MiB/CCX, up to 256 MiB total
 
** "{{amd|Vermeer|l=core}}": 32 MiB/CCX, up to 64 MiB total
 
** "{{amd|Vermeer|l=core}}": 32 MiB/CCX, up to 64 MiB total
 
** "{{amd|Cezanne|l=core}}": 16 MiB, 8 MiB usable on some SKUs
 
** "{{amd|Cezanne|l=core}}": 16 MiB, 8 MiB usable on some SKUs
** Shared by all cores in the {{abbr|CCX}}, configurable<ref name="amd-56375-qos"/>
+
** Shared by all cores in the CCX, configurable<ref name="amd-56375-qos">{{cite techdoc|title=AMD64 Technology Platform Quality of Service Extensions|url=https://developer.amd.com/wp-content/resources/56375.pdf|publ=AMD|pid=56375|rev=1.02|date=2020-10}}</ref>
 
** 16-way set associative
 
** 16-way set associative
 
** 64 B line size
 
** 64 B line size
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** Write-back policy
 
** Write-back policy
 
** 46 cycles average load-to-use latency
 
** 46 cycles average load-to-use latency
** DEC-TED ECC, tag array & shadow tags SEC-DED<!--AMD-55898-0.50 Sec 3.5-->
+
** ECC
 
** QoS Monitoring and Enforcement V2.0
 
** QoS Monitoring and Enforcement V2.0
  
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==== System DRAM ====
 
==== System DRAM ====
 
* EPYC 7003 "{{amd|Milan|l=core}}":
 
* EPYC 7003 "{{amd|Milan|l=core}}":
** 8 channels per socket, up to 16 DIMMs, max. 4&nbsp;TiB
+
** 8 channels per socket, up to 16 DIMMs, max. 4 TiB
** Up to PC4-25600L (DDR4-3200)
+
** Up to PC4-25600L (DDR4-3200), ECC supported
** {{abbr|SR}}/{{abbr|DR}} {{abbr|RDIMM}}, {{abbr|4R}}/{{abbr|8R}} {{abbr|LRDIMM}}, {{abbr|3DS DIMM}}, {{abbr|NVDIMM-N}}
+
** SR/DR RDIMM, 4R/8R LRDIMM, 3DS DIMM, NVDIMM-N
** ECC supported (x4, x8, x16, chipkill)<!--AMD-55898-0.50 Sec 3.7-->
 
** DRAM bus parity and write data CRC options<!--ibid-->
 
 
 
* Ryzen Threadripper 5900 "{{amd|Chagall|l=core}}":
 
** 8 channels, up to 8 DIMMs, max. 2&nbsp;TiB
 
** Up to PC4-25600L (DDR4-3200)
 
** SR/DR {{abbr|UDIMM}}, RDIMM, LRDIMM, 3DS DIMM
 
** ECC supported
 
 
 
 
* Ryzen 5000 "{{amd|Vermeer|l=core}}":
 
* Ryzen 5000 "{{amd|Vermeer|l=core}}":
** 2 channels, up to 4 DIMMs, max. 128&nbsp;GiB
+
** 2 channels, up to 4 DIMMs, max. 128 GiB
 
** Up to PC4-25600U (DDR4-3200 UDIMM), ECC supported
 
** Up to PC4-25600U (DDR4-3200 UDIMM), ECC supported
 
 
* Ryzen 5000 APU "{{amd|Cezanne|l=core}}":
 
* Ryzen 5000 APU "{{amd|Cezanne|l=core}}":
** {{amd|Socket AM4|l=pack}}:
+
** DDR4-3200 or LPDDR4-4266
*** 2 channels, up to 4 DIMMs, max. 128&nbsp;GiB
 
*** Up to PC4-25600U (DDR4-3200 UDIMM), ECC supported ("PRO" models)
 
** {{amd|FP6|FP6 package|l=pack}}, DDR4 mode:
 
*** 2 × 64-bit channels, up to 2 DIMMs, max. 64&nbsp;GiB
 
*** Up to PC4-25600U (DDR4-3200 UDIMM), ECC supported(?)
 
** FP6 package, LPDDR4 mode:
 
*** 4 × 32-bit channels, max. 32&nbsp;GiB
 
*** Up to LPDDR4X-4266
 
  
Sources: <ref name="amd-56375-qos"/><ref name="amd-56665-sog-19h"/><ref name="amd-55898-ppr-1901-0.35"/><ref name="amd-55898-ppr-1901-0.50"/><ref name="amd-56178-mdg-fp6"/>
+
Sources:<ref name="amd-56375-qos"/><ref name="amd-56665-sog-19h">{{cite techdoc|title=Software Optimization Guide for AMD Family 19h Processors (PUB)|url=https://www.amd.com/system/files/TechDocs/56665.zip|publ=AMD|pid=56665|rev=3.00|date=2020-11}}</ref><ref name="amd-55898-ppr-1901">{{cite techdoc|title=Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors|url=https://www.amd.com/system/files/TechDocs/55898_pub.zip|publ=AMD|pid=55898|rev=0.35|date=2021-02-05}}</ref>
  
 
== All Zen 3 Chips ==
 
== All Zen 3 Chips ==
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== References ==
 
== References ==
<references>
+
<references/>
<ref name="amd-psf">{{cite techdoc|title=White Paper: Security Analysis of AMD Predictive Store Forwarding|url=https://www.amd.com/system/files/documents/security-analysis-predictive-store-forwarding.pdf|publ=AMD|date=2021-03}}</ref>
 
<ref name="amd-24593-apm2">{{cite techdoc|title=AMD64 Architecture Programmer’s Manual Volume 2: System Programming|url=https://www.amd.com/system/files/TechDocs/24593.pdf|publ=AMD|pid=24593|rev=3.37|date=2021-03}}</ref>
 
<ref name="amd-24594-apm3">{{cite techdoc|title=AMD64 Architecture Programmer’s Manual Volume 3: General-Purpose and System Instructions|url=https://www.amd.com/system/files/TechDocs/24594.pdf|publ=AMD|pid=24594|rev=3.32|date=2021-03}}</ref>
 
<ref name="amd-26568-apm4">{{cite techdoc|title=AMD64 Architecture Programmer’s Manual Volume 4: 128-Bit and 256-Bit Media Instructions|url=https://www.amd.com/system/files/TechDocs/26568.pdf|publ=AMD|pid=26568|rev=3.24|date=2020-05}}</ref>
 
<ref name="amd-56375-qos">{{cite techdoc|title=AMD64 Technology Platform Quality of Service Extensions|url=https://developer.amd.com/wp-content/resources/56375.pdf|publ=AMD|pid=56375|rev=1.02|date=2020-10}}</ref>
 
<ref name="amd-56665-sog-19h">{{cite techdoc|title=Software Optimization Guide for AMD Family 19h Processors (PUB)|url=https://www.amd.com/system/files/TechDocs/56665.zip|publ=AMD|pid=56665|rev=3.00|date=2020-11}}</ref>
 
<ref name="amd-55898-ppr-1901-0.35">{{cite techdoc|title=Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors|url=https://www.amd.com/system/files/TechDocs/55898_pub.zip|publ=AMD|pid=55898|rev=0.35|date=2021-02-05}}</ref>
 
<ref name="amd-55898-ppr-1901-0.50">{{cite techdoc|title=Preliminary Processor Programming Reference (PPR) for AMD Family 19h Model 01h, Revision B1 Processors|publ=AMD|pid=55898|rev=0.50|date=2021-05-27}}</ref>
 
<ref name="amd-56178-mdg-fp6">{{cite techdoc|title=FP6 Processor Motherboard Design Guide|publ=AMD|pid=56178|rev=1.03|date=2020-01}}</ref>
 
</references>
 
  
 
== See Also ==
 
== See Also ==
* AMD {{\\|Zen}}, {{\\|Zen 2}}, {{\\|Zen 4}}
+
* AMD {{\\|Zen}}, {{\\|Zen 2}}
 
* Intel {{intel|Tigerlake|l=arch}}
 
* Intel {{intel|Tigerlake|l=arch}}
 
* Read also: [https://www.anandtech.com/print/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested AMD Zen 3 Ryzen Deep Dive Review]
 
* Read also: [https://www.anandtech.com/print/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested AMD Zen 3 Ryzen Deep Dive Review]
 
* Read here: [https://techmotherboard.com/best-zen-3-cpu/ AMD Zen 3 Reviews]
 
* Read here: [https://techmotherboard.com/best-zen-3-cpu/ AMD Zen 3 Reviews]

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codenameZen 3 +
core count64 +, 56 +, 48 +, 32 +, 28 +, 24 +, 16 +, 12 +, 8 + and 6 +
designerAMD +
first launchedOctober 8, 2020 +
full page nameamd/microarchitectures/zen 3 +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerTSMC + and GlobalFoundries +
microarchitecture typeCPU +
nameZen 3 +
pipeline stages19 +