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|introduction=October 8, 2020
 
|introduction=October 8, 2020
 
|process=7nm
 
|process=7nm
|cores=64
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|process 2=12 nm
|cores 2=48
 
|cores 3=32
 
|cores 4=16
 
|cores 5=12
 
|cores 6=8
 
|cores 7=6
 
 
|type=Superscalar
 
|type=Superscalar
 
|oooe=Yes
 
|oooe=Yes
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|successor link=amd/microarchitectures/zen 4
 
|successor link=amd/microarchitectures/zen 4
 
}}
 
}}
'''Zen 3''' is a [[microarchitecture]] developed by [[AMD]] as a successor to {{\\|Zen 2}}. It was publicly released on October 8, 2020. Mainstream Desktop processors hit shelves on November 5, 2020.
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'''Zen 3''' is a planned [[microarchitecture]] being developed by [[AMD]] as a successor to {{\\|Zen 2}}.
  
 
== History ==
 
== History ==
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! Core !! C/T !! Target
 
! Core !! C/T !! Target
 
|-
 
|-
| {{amd|Milan|l=core}} || Up to 64/128 || High-end server [[multiprocessors]]
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| {{amd|Milan|l=core}} || 64/128 || High-end server [[multiprocessors]]
 
|-
 
|-
 
| {{amd|Genesis Peak|l=core}} || ?/? || Workstation & enthusiasts market processors
 
| {{amd|Genesis Peak|l=core}} || ?/? || Workstation & enthusiasts market processors
 
|-
 
|-
| {{amd|Vermeer|l=core}} || Up to 16/32 || Mainstream to high-end desktops & enthusiasts market processors
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| {{amd|Vermeer|l=core}} || 16/32 || Mainstream to high-end desktops & enthusiasts market processors
 
|-
 
|-
| {{amd|Cezanne|l=core}} || Up to 8/16 || Mainstream desktop & mobile processors with GPU  
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| {{amd|Cezanne|l=core}} || ?/? || Mainstream desktop & mobile processors with GPU  
 
|}
 
|}
  
 
== Process technology ==
 
== Process technology ==
Zen 3 will be fabricated on [[TSMC]]'s [[7 nm process|7nm+ process]], the same process used in Zen 2 Refresh processors.  
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Zen 3 will be fabricated on [[TSMC]]'s [[7 nm process|7nm+ process]].
  
 
== Architecture ==
 
== Architecture ==
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=== Key changes from {{\\|Zen 2}} ===
 
=== Key changes from {{\\|Zen 2}} ===
* CCD
+
 
** Unified 8-core CCX (from 2x 4-Core CCX per CCD)
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* Unified 8-core CCX with 32 MiB L3$ available to all 8 cores equally
** 32 MiB L3$ available equally to all cores in CCD.
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*** Increased L3 latency (~46 cycles, up from ~40 cycles)
+
* Wider and more flexible issue in floating-point and integer engines
* Core
+
 
** Higher [[IPC]] (AMD self-reported +19% IPC)
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* Increased number of loads and stores, improved prefetching
** Front-end
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** Increased branch prediction bandwidth
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* Increased branch prediction bandwidth, "zero-bubble" branch prediction
*** "zero-bubble" branch prediction
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*** L1 BTB doubled from 512 to 1024 entries
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* Improved µop cache
** Improved prefetching
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** Improved µop cache
 
* Back-end
 
** Floating point unit:
 
*** FMA latency reduced by 1 cycle from 5 to 4.
 
*** Fifth and sixth dedicated execution ports added for floating point store and FP-to-int transfer, no longer sharing 2nd FADD port.
 
*** Unified scheduler split into 1 scheduler per FMA/FADD/transfer port set.
 
*** 256b VAES and VPCLMULDQ support for doubled AES and AES-GCM cryptographic throughout.
 
*** Hardware implementation of BMI2 PDEP/PEXT bit scatter/gather operations, compared to prior microcode emulation.
 
** Integer unit:
 
*** Integer physical register file increased from 180 to 192 entries
 
*** Issue increased from 7 (existing 4 ALU and 3 AGU) to 10 with 1 new dedicated branch execution port and 2 separated store data pathways.
 
*** Schedulers shared between pairs of ALU + AGU/branch ports instead of dedicated for each.
 
*** Instruction redundancy increased between ports for reduced bottlenecking on a wider variety of instruction streams.
 
*** 8/16/32/64 bit signed integer division/modulo latency improved from 17/22/30/46 cycles to 10/12/14/20. (Unsigned operations are ~1 cycle faster for some of both old/new cases.) Throughput improves proportionately.
 
** Load/store:
 
*** Load throughput increased from 2 to 3, if not 256b.
 
*** Store throughput increased from 1 to 2, if not 256b.
 
*** Store queue increase from 48 to 64 slots.
 
*** Page table walkers tripled from 2 to 6 for TLB miss handling.
 
 
{{expand list}}
 
{{expand list}}
  
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== Designers ==
 
== Designers ==
* Mark Evers, Chief Architect
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* Leslie Barnes, chief architect
  
 
== Bibliography ==
 
== Bibliography ==
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* AMD {{\\|Zen}}
 
* AMD {{\\|Zen}}
 
* Intel {{intel|Tigerlake|l=arch}}
 
* Intel {{intel|Tigerlake|l=arch}}
* Read also: [https://www.anandtech.com/print/16214/amd-zen-3-ryzen-deep-dive-review-5950x-5900x-5800x-and-5700x-tested AMD Zen 3 Ryzen Deep Dive Review]
 
* Read here: [https://techmotherboard.com/best-zen-3-cpu/ AMD Zen 3 Reviews]
 

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codenameZen 3 +
core count64 +, 48 +, 32 +, 16 +, 12 +, 8 + and 6 +
designerAMD +
first launchedOctober 8, 2020 +
full page nameamd/microarchitectures/zen 3 +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerTSMC + and GlobalFoundries +
microarchitecture typeCPU +
nameZen 3 +
pipeline stages19 +
process7 nm (0.007 μm, 7.0e-6 mm) +