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Difference between revisions of "amd/microarchitectures/zen 2"
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== Architecture ==
 
== Architecture ==
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Nothing concrete is currently known about the architectural improvements that is being done to Zen 2.
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{{work-in-progress}}
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Papermaster's presentation at Next Horizon quotes "Improved Branch Predictor", "Better Instruction Pre-Fetching", "Re-Optimized Instruction Cache", "Larger Op Cache", "Doubled Floating Point Width to 256-bit", "Doubled Load / Store Bandwidth", "Increased Dispatch / Retire Bandwidth", "Maintained High Throughput for All Modes" without further specifics.
 
  
 
=== Key changes from {{\\|Zen}} ===
 
=== Key changes from {{\\|Zen}} ===

Revision as of 18:50, 12 November 2018

Edit Values
Zen 2 µarch
General Info
Arch TypeCPU
DesignerAMD
ManufacturerTSMC
Introduction2019
Process7 nm
Succession

Zen 2 is a planned microarchitecture being developed by AMD as a successor to Zen+. Zen 2 is expected to be succeeded by Zen 3.

History

amd zen future roadmap.jpg

Zen 2 is set to succeed Zen in the future, sometimes around 2019. In February of 2017 Lisa Su, AMD's CEO announced their future roadmap to include Zen 2 and later Zen 3. On Investor's Day May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 2 is set to utilize 7 nm process.

Codenames

amd zen2-3 roadmap.png
Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Core C/T Target
Rome Up to 64/128 High-end server multiprocessors
Castle Peak  ?/? workstation & enthusiasts market processors
Matisse  ?/? Mainstream to high-end desktops & enthusiasts market processors
Picasso  ?/? Mainstream desktop & mobile processors with GPU

Process technology

Zen 2 is fabricated on TSMC's 7 nm process.

Compiler support

Compiler Arch-Specific Arch-Favorable
GCC -march=znver2 -mtune=znver2
  • Note: Initial support in GCC 9.

Architecture

Under construction icon-blue.svg This article is a work in progress!

Key changes from Zen

This list is incomplete; you can help by expanding it.

New instructions

Zen 2 introduced a number of new x86 instructions:

  • CLWB - Force cache line write-back without flush
  • RDPID - Read Processor ID
  • WBNOINVD - Force cache line write-back without invalidation

Bibliography

  • AMD 'Tech Day', February 22, 2017
  • AMD 2017 Financial Analyst Day, May 16, 2017
  • AMD GCC 9 znver2 enablement patch
  • AMD 'Next Horizon', November 6, 2018

See Also

Retrieved from "https://en.wikichip.org/w/index.php?title=amd/microarchitectures/zen_2&oldid=84007"
Facts about "Zen 2 - Microarchitectures - AMD"
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codenameZen 2 +
designerAMD +
first launched2019 +
full page nameamd/microarchitectures/zen 2 +
instance ofmicroarchitecture +
manufacturerTSMC +
microarchitecture typeCPU +
nameZen 2 +
process7 nm (0.007 μm, 7.0e-6 mm) +