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This image originates from a slide presented at AMD EPYC Tech Day, June 20, 2017 and shows one layer of die interconnects on the EPYC package substrate. The pink lines fanning out at the top and bottom connect to the UMCs on the respective chip. The light blue and pink lines in the center are bidirectional GMI links. The UMC connections of the top left and bottom right chip, the GMI link from the bottom left to the top right chip, and the PCIe connections are not visible in this picture. Of the four GMI interfaces on each die only the three closest to the other dies are used. It should be noted that its creator pasted Zeppelin die shots onto the image and improperly reflected the top left and bottom right chip. In reality four identical dies are used, with the top left chip mounted in the same orientation as the top right chip, and both bottom chips rotated by 180 degrees.</div>
 
This image originates from a slide presented at AMD EPYC Tech Day, June 20, 2017 and shows one layer of die interconnects on the EPYC package substrate. The pink lines fanning out at the top and bottom connect to the UMCs on the respective chip. The light blue and pink lines in the center are bidirectional GMI links. The UMC connections of the top left and bottom right chip, the GMI link from the bottom left to the top right chip, and the PCIe connections are not visible in this picture. Of the four GMI interfaces on each die only the three closest to the other dies are used. It should be noted that its creator pasted Zeppelin die shots onto the image and improperly reflected the top left and bottom right chip. In reality four identical dies are used, with the top left chip mounted in the same orientation as the top right chip, and both bottom chips rotated by 180 degrees.</div>
 
{{clear}}
 
{{clear}}
 
==== Die-die memory latencies ====
 
The following is the average die-to-die latencies across two dies over the {{amd|infinity fabric}} on the [[EPYC 7601]] (32-core, 2.2 GHz) using 16 DDR4-2666 DIMMS.
 
 
<table class="wikitable">
 
<tr><th colspan="9">Die-to-die Latency</th></tr>
 
<tr><th>Die</th><td>0</td><td>1</td><td>2</td><td>3</td><td>4</td><td>5</td><td>6</td><td>7</td></tr>
 
<tr><td>0</td><td style="background-color: #63f800;">85 ns</td><td style="background-color: #f2f800;">140 ns</td><td style="background-color: #daf800;">135 ns</td><td style="background-color: #daf800;">135 ns</td><td style="background-color: #f81700;">245 ns</td><td style="background-color: #f81700;">245 ns</td><td style="background-color: #f86f00;">200 ns</td><td style="background-color: #f84000;">235 ns</td></tr>
 
<tr><td>1</td><td style="background-color: #f2f800;">140 ns</td><td style="background-color: #63f800;">85 ns</td><td style="background-color: #daf800;">135 ns</td><td style="background-color: #daf800;">135 ns</td><td style="background-color: #f81700;">245 ns</td><td style="background-color: #f82f00;">240 ns</td><td style="background-color: #f84000;">235 ns</td><td style="background-color: #f86f00;">200 ns</td></tr>
 
<tr><td>2</td><td style="background-color: #daf800;">135 ns</td><td style="background-color: #c6f800;">130 ns</td><td style="background-color: #63f800;">85 ns</td><td style="background-color: #f2f800;">140 ns</td><td style="background-color: #f86f00;">200 ns</td><td style="background-color: #f80000;">250 ns</td><td style="background-color: #f84000;">235 ns</td><td style="background-color: #f84000;">235 ns</td></tr>
 
<tr><td>3</td><td style="background-color: #daf800;">135 ns</td><td style="background-color: #c6f800;">130 ns</td><td style="background-color: #f2f800;">140 ns</td><td style="background-color: #63f800;">85 ns</td><td style="background-color: #f80000;">250 ns</td><td style="background-color: #f86f00;">200 ns</td><td style="background-color: #f84000;">235 ns</td><td style="background-color: #f84000;">235 ns</td></tr>
 
<tr><td>4</td><td style="background-color: #f82f00;">240 ns</td><td style="background-color: #f82f00;">240 ns</td><td style="background-color: #f86f00;">200 ns</td><td style="background-color: #f82f00;">240 ns</td><td style="background-color: #63f800;">85 ns</td><td style="background-color: #f2f800;">140 ns</td><td style="background-color: #daf800;">135 ns</td><td style="background-color: #daf800;">135 ns</td></tr>
 
<tr><td>5</td><td style="background-color: #f82f00;">240 ns</td><td style="background-color: #f82f00;">240 ns</td><td style="background-color: #f84000;">235 ns</td><td style="background-color: #f86f00;">200 ns</td><td style="background-color: #f2f800;">140 ns</td><td style="background-color: #63f800;">85 ns</td><td style="background-color: #daf800;">135 ns</td><td style="background-color: #daf800;">135 ns</td></tr>
 
<tr><td>6</td><td style="background-color: #f86f00;">200 ns</td><td style="background-color: #f81700;">245 ns</td><td style="background-color: #f84000;">235 ns</td><td style="background-color: #f84000;">235 ns</td><td style="background-color: #daf800;">135 ns</td><td style="background-color: #daf800;">135 ns</td><td style="background-color: #63f800;">85 ns</td><td style="background-color: #f2f800;">140 ns</td></tr>
 
<tr><td>7</td><td style="background-color: #f81700;">245 ns</td><td style="background-color: #f86f00;">200 ns</td><td style="background-color: #f84000;">235 ns</td><td style="background-color: #f84000;">235 ns</td><td style="background-color: #daf800;">135 ns</td><td style="background-color: #daf800;">135 ns</td><td style="background-color: #f2f800;">140 ns</td><td style="background-color: #63f800;">85 ns</td></tr>
 
</table>
 
  
 
=== Modules (Zeppelin) ===
 
=== Modules (Zeppelin) ===

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codenameZen +
core count4 +, 6 +, 8 +, 16 +, 24 +, 32 + and 12 +
designerAMD +
first launchedMarch 2, 2017 +
full page nameamd/microarchitectures/zen +
instance ofmicroarchitecture +
instruction set architecturex86-64 +
manufacturerGlobalFoundries +
microarchitecture typeCPU +
nameZen +
pipeline stages19 +
process14 nm (0.014 μm, 1.4e-5 mm) +