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Latest revision | Your text | ||
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=== Key changes from {{\\|Excavator}} === | === Key changes from {{\\|Excavator}} === | ||
− | * Zen was designed to succeed | + | * Zen was designed to succeed BOTH {{\\|Excavator}} (High-performance) and {{\\|Puma}} (Low-power) covering the entire range in one architecture |
** Cover the entire spectrum from fanless notebooks to high-performance desktops | ** Cover the entire spectrum from fanless notebooks to high-performance desktops | ||
** More aggressive clock gating with multi-level regions | ** More aggressive clock gating with multi-level regions | ||
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** From {{\\|Piledriver}} to Zen | ** From {{\\|Piledriver}} to Zen | ||
** Based on the industry-standardized SPECint_base2006 score compiled with GCC 4.6 -O2 at a fixed 3.4GHz | ** Based on the industry-standardized SPECint_base2006 score compiled with GCC 4.6 -O2 at a fixed 3.4GHz | ||
− | * Up to 3. | + | * Up to 3.7x performance/watt improvment |
* Return to conventional high-performance x86 design | * Return to conventional high-performance x86 design | ||
** Traditional design for cores without shared blocks (e.g. shared SIMD units) | ** Traditional design for cores without shared blocks (e.g. shared SIMD units) | ||
** Large beefier core design | ** Large beefier core design | ||
* Core engine | * Core engine | ||
− | ** Simultaneous Multithreading (SMT) support, 2 threads/core (see [[# | + | ** Simultaneous Multithreading (SMT) support, 2 threads/core (see [[#Simultaneous_MultiThreading_.28SMT.29|§ Simultaneous MultiThreading]] for details) |
** Branch Predictor | ** Branch Predictor | ||
*** Improved branch mispredictions | *** Improved branch mispredictions | ||
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**** Lower miss latency penalty | **** Lower miss latency penalty | ||
*** BP is now decoupled from fetch stage | *** BP is now decoupled from fetch stage | ||
− | ** Large | + | ** Large Op cache (2K instructions) |
** Wider μop dispatch (6, up from 4) | ** Wider μop dispatch (6, up from 4) | ||
** Larger instruction scheduler | ** Larger instruction scheduler | ||
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*** 64 KiB (double from previous capacity of 32 KiB) | *** 64 KiB (double from previous capacity of 32 KiB) | ||
*** Write-back L1 cache eviction policy (From write-through) | *** Write-back L1 cache eviction policy (From write-through) | ||
− | *** | + | *** 2x the bandwidth |
** L2 | ** L2 | ||
− | *** | + | *** 2x the bandwidth |
*** Faster L2 cache | *** Faster L2 cache | ||
** Faster L3 cache | ** Faster L3 cache | ||
+ | ** Large Op cache | ||
** Better L1$ and L2$ data prefetcher | ** Better L1$ and L2$ data prefetcher | ||
− | ** | + | ** 5x L3 bandwidth |
** Move elimination block added | ** Move elimination block added | ||
** Page Table Entry (PTE) Coalescing | ** Page Table Entry (PTE) Coalescing |
Facts about "Zen - Microarchitectures - AMD"
codename | Zen + |
core count | 4 +, 6 +, 8 +, 16 +, 24 +, 32 + and 12 + |
designer | AMD + |
first launched | March 2, 2017 + |
full page name | amd/microarchitectures/zen + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | Zen + |
pipeline stages | 19 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |