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==== Enhanced power gating ==== | ==== Enhanced power gating ==== | ||
− | [[File:raven ridge power regions.png|right| | + | [[File:raven ridge power regions.png|right|450px]] |
Raven Ridge incorporates an enhanced power gating scheme to lower the average power consumption of the chip. Upon exiting [[P-State]], the CPU enters the [[C-state|CC6 Idle State]]. When all the CPU cores enter CC6, the ''CPUOFF'' state is asserted and the shared [[L3 cache]] power is lowered. Likewise, when the GPU enters idle state, up to 95% of the GPU is power gated. A ''GPUOFF'' state further power down the GPU uncore. When both ''CPUOFF'' and ''GPUOFF'' states are asserted, the system VDD regulator is switched off. | Raven Ridge incorporates an enhanced power gating scheme to lower the average power consumption of the chip. Upon exiting [[P-State]], the CPU enters the [[C-state|CC6 Idle State]]. When all the CPU cores enter CC6, the ''CPUOFF'' state is asserted and the shared [[L3 cache]] power is lowered. Likewise, when the GPU enters idle state, up to 95% of the GPU is power gated. A ''GPUOFF'' state further power down the GPU uncore. When both ''CPUOFF'' and ''GPUOFF'' states are asserted, the system VDD regulator is switched off. | ||
Facts about "Zen - Microarchitectures - AMD"
codename | Zen + |
core count | 4 +, 6 +, 8 +, 16 +, 24 +, 32 + and 12 + |
designer | AMD + |
first launched | March 2, 2017 + |
full page name | amd/microarchitectures/zen + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | Zen + |
pipeline stages | 19 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |