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** 2x Unified Memory Controllers (UMC) - one DRAM channel each; 64-bit data + [[ECC]] support, 2 DIMMs, DDR4 1333MT/s-3200MT/s | ** 2x Unified Memory Controllers (UMC) - one DRAM channel each; 64-bit data + [[ECC]] support, 2 DIMMs, DDR4 1333MT/s-3200MT/s | ||
* PSP (MP0) and SMU (MP1) microcontrollers | * PSP (MP0) and SMU (MP1) microcontrollers | ||
− | ** AMD Secure Processor | + | ** AMD Secure Processor technology as Platform Security Processor (PSP) |
− | |||
* NBIO | * NBIO | ||
** 2 SYSHUBs, 1 IOHUB with IOMMU v2.x | ** 2 SYSHUBs, 1 IOHUB with IOMMU v2.x | ||
** 2x8 PCIe Gen1/Gen2/Gen3 | ** 2x8 PCIe Gen1/Gen2/Gen3 | ||
* 6 x4 PHYs plus 5 x2 PHYs | * 6 x4 PHYs plus 5 x2 PHYs | ||
− | ** Support PCIe, WAFL, | + | ** Support PCIe, WAFL, [[infinity_fabric|Global Memory Interconnect]] (xGMI), SATA, and Ethernet |
*** Ethernet complex: Up to 4 lanes of 10/100/1000 SGMII, or 10GBASE-KR, or 1000BASE-KX Ethernet operation | *** Ethernet complex: Up to 4 lanes of 10/100/1000 SGMII, or 10GBASE-KR, or 1000BASE-KX Ethernet operation | ||
* Southbridge | * Southbridge |
Facts about "Zen - Microarchitectures - AMD"
codename | Zen + |
core count | 4 +, 6 +, 8 +, 16 +, 24 +, 32 + and 12 + |
designer | AMD + |
first launched | March 2, 2017 + |
full page name | amd/microarchitectures/zen + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | Zen + |
pipeline stages | 19 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |