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== Scalability == | == Scalability == | ||
=== CPU Complex (CCX) === | === CPU Complex (CCX) === | ||
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AMD organized Zen in groups of cores called a '''CPU Complex''' ('''CCX'''). Each CCX consists of four cores connected to an L3 cache. The L3 cache is an 8 MiB 16-way set associative [[victim cache]] and is mostly [[exclusive cache|exclusive]] of the L2. The L3 cache is made of four slices (providing 2 MiB L3 slice/core) organized by low-order address interleaved. Every core can access every L3 cache slice with the same average latency. When a certain core starts working on a chunk of memory it will fill up the L2 and as it continue to execute and fetch new data any spillover will find its way in the L3. | AMD organized Zen in groups of cores called a '''CPU Complex''' ('''CCX'''). Each CCX consists of four cores connected to an L3 cache. The L3 cache is an 8 MiB 16-way set associative [[victim cache]] and is mostly [[exclusive cache|exclusive]] of the L2. The L3 cache is made of four slices (providing 2 MiB L3 slice/core) organized by low-order address interleaved. Every core can access every L3 cache slice with the same average latency. When a certain core starts working on a chunk of memory it will fill up the L2 and as it continue to execute and fetch new data any spillover will find its way in the L3. | ||
Facts about "Zen - Microarchitectures - AMD"
codename | Zen + |
core count | 4 +, 6 +, 8 +, 16 +, 24 +, 32 + and 12 + |
designer | AMD + |
first launched | March 2, 2017 + |
full page name | amd/microarchitectures/zen + |
instance of | microarchitecture + |
instruction set architecture | x86-64 + |
manufacturer | GlobalFoundries + |
microarchitecture type | CPU + |
name | Zen + |
pipeline stages | 19 + |
process | 14 nm (0.014 μm, 1.4e-5 mm) + |