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Latest revision | Your text | ||
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* System Bus | * System Bus | ||
** K7 utilizes the [[Digital Alpha]] {{decc|EV6}} system bus interface | ** K7 utilizes the [[Digital Alpha]] {{decc|EV6}} system bus interface | ||
− | *** AMD licensed the technology from Digital allowing them to independently develop their own [[chipsets]] and [[motherboards]] without paying licensing | + | *** AMD licensed the technology from Digital allowing them to independently develop their own [[chipsets]] and [[motherboards]] without paying licensing frees to [[Intel]] for their [[Slot 1]] {{intel|GTL+}} bus. This does consequently meant incompatibility AMD's motherboards and Intel's motherboards. |
*** The EV6 utilizes [[double data rate]] (DDR) doubling the effective data transfer rate of the bus speed. | *** The EV6 utilizes [[double data rate]] (DDR) doubling the effective data transfer rate of the bus speed. | ||
*** 100 MHz bus = 200 [[MT/s]] | *** 100 MHz bus = 200 [[MT/s]] |
Facts about "K7 - Microarchitectures - AMD"
codename | K7 + |
core count | 1 + |
designer | AMD + |
first launched | June 23, 1999 + |
full page name | amd/microarchitectures/k7 + |
instance of | microarchitecture + |
instruction set architecture | x86-32 + |
manufacturer | AMD + |
microarchitecture type | CPU + |
name | K7 + |
pipeline stages (max) | 15 + |
pipeline stages (min) | 10 + |
process | 250 nm (0.25 μm, 2.5e-4 mm) +, 180 nm (0.18 μm, 1.8e-4 mm) + and 130 nm (0.13 μm, 1.3e-4 mm) + |