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Both AMD's and Intel's original models did not feature on-die L2$. When compared to [[Intel]]'s original {{intel|Pentium III}} L1 which was 32 KiB (albeit at higher associativity), K7 had superior performance due to having 4 times as much cache. By the following year AMD moved the cach on-die. With the introduction of the {{intel|Coppermine}} models, Intel moved the L2$ on-die as well with half of K7's latency. This change allowed Pentium models to outperform Athlon for certain workloads. | Both AMD's and Intel's original models did not feature on-die L2$. When compared to [[Intel]]'s original {{intel|Pentium III}} L1 which was 32 KiB (albeit at higher associativity), K7 had superior performance due to having 4 times as much cache. By the following year AMD moved the cach on-die. With the introduction of the {{intel|Coppermine}} models, Intel moved the L2$ on-die as well with half of K7's latency. This change allowed Pentium models to outperform Athlon for certain workloads. |
Facts about "K7 - Microarchitectures - AMD"
codename | K7 + |
core count | 1 + |
designer | AMD + |
first launched | June 23, 1999 + |
full page name | amd/microarchitectures/k7 + |
instance of | microarchitecture + |
instruction set architecture | x86-32 + |
manufacturer | AMD + |
microarchitecture type | CPU + |
name | K7 + |
pipeline stages (max) | 15 + |
pipeline stages (min) | 10 + |
process | 250 nm (0.25 μm, 2.5e-4 mm) +, 180 nm (0.18 μm, 1.8e-4 mm) + and 130 nm (0.13 μm, 1.3e-4 mm) + |