Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "amd/microarchitectures/bulldozer"
| Line 8: | Line 8: | ||
| phase-out = | | phase-out = | ||
| process = 32 nm | | process = 32 nm | ||
| − | |isa | + | |isa=x86-64 |
| − | |||
| − | |||
| succession = Yes | | succession = Yes | ||
| predecessor = K10 | | predecessor = K10 | ||
Revision as of 19:59, 30 November 2017
| Edit Values | |
| Bulldozer µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | AMD |
| Manufacturer | AMD |
| Introduction | October 12, 2011 |
| Process | 32 nm |
| Instructions | |
| ISA | x86-64 |
| Succession | |
Bulldozer was the microarchitecture developed by AMD as a successor to K10. K10 was superseded by Piledriver in 2011.
Architecture
 |
This section is empty; you can help add the missing info by editing this page. |
Die Shot
All Bulldozer Chips
| Bulldozer Chips | ||||||
|---|---|---|---|---|---|---|
| Model | Family | Core | Launched | Power Dissipation | Freq | Max Mem |
| Count: 0 | ||||||
See also
Facts about "Bulldozer - Microarchitectures - AMD"
| codename | Bulldozer + |
| designer | AMD + |
| first launched | October 12, 2011 + |
| full page name | amd/microarchitectures/bulldozer + |
| instance of | microarchitecture + |
| instruction set architecture | x86-64 + |
| manufacturer | AMD + |
| microarchitecture type | CPU + |
| name | Bulldozer + |
| process | 32 nm (0.032 μm, 3.2e-5 mm) + |
