From WikiChip
Difference between revisions of "amd/k6/amd-k6/233bcz"
< amd‎ | k6

(+documents)
(Cache)
Line 76: Line 76:
 
== Cache ==
 
== Cache ==
 
{{main|amd/microarchitectures/k6#Memory_Hierarchy|l1=K6 § Cache}}
 
{{main|amd/microarchitectures/k6#Memory_Hierarchy|l1=K6 § Cache}}
[[L2$]] can be 256 KB to 1 MB, depending on manufacturer and [[motherboard]] model. L2$ is off-chip.
+
[[L2$]] can be 256 KiB to 1 MiB, depending on manufacturer and [[motherboard]] model. L2$ is off-chip.
 
{{cache info
 
{{cache info
|l1i cache=32 KB
+
|l1i cache=32 KiB
|l1i break=1x32 KB
+
|l1i break=1x32 KiB
 
|l1i desc=2-way set associative
 
|l1i desc=2-way set associative
 
|l1i extra=
 
|l1i extra=
|l1d cache=32 KB
+
|l1d cache=32 KiB
|l1d break=1x32 KB
+
|l1d break=1x32 KiB
 
|l1d desc=2-way set associative
 
|l1d desc=2-way set associative
 
|l1d extra=
 
|l1d extra=

Revision as of 00:18, 21 September 2016

Template:mpu AMD-K6/233BCZ was a 32-bit x86 mobile microprocessor designed by AMD and introduced in early 1998. This chip, which was based on AMD's new K6 microarchitecture, operated at 233 MHz and dissipated a maximum of 9 W.

Cache

Main article: K6 § Cache

L2$ can be 256 KiB to 1 MiB, depending on manufacturer and motherboard model. L2$ is off-chip.

Cache Info [Edit Values]
L1I$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative
L1D$ 32 KiB
32,768 B
0.0313 MiB
1x32 KiB 2-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Auto-power down state
  • Stop clock state

Documents

DataSheet

Facts about "AMD-K6/233BCZ - AMD"
l1d$ description2-way set associative +
l1d$ size32 KiB (32,768 B, 0.0313 MiB) +
l1i$ description2-way set associative +
l1i$ size32 KiB (32,768 B, 0.0313 MiB) +