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Difference between revisions of "amd/k6-2/k6-2-500afx"
< amd‎ | k6-2

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'''K6-2/500AFX''' was a {{arch|32}} [[x86]] {{amd|microarchitectures/k6-2|K6-2}}-based microprocessor designed and manufactured in [[1999]] by [[AMD]]. Manufactured using a [[0.25 µm process]], this MPU operated at 500 MHz with a [[FSB]] of 100 MHz consumed 20.7 W.
 
'''K6-2/500AFX''' was a {{arch|32}} [[x86]] {{amd|microarchitectures/k6-2|K6-2}}-based microprocessor designed and manufactured in [[1999]] by [[AMD]]. Manufactured using a [[0.25 µm process]], this MPU operated at 500 MHz with a [[FSB]] of 100 MHz consumed 20.7 W.
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== Cache ==
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{{main|amd/microarchitectures/k6-2#Memory_Hierarchy|l1=K6-2 § Cache}}
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[[L2$]] can be 512 KB to 2 MB, depending on manufacturer and [[motherboard]] model. L2$ is off-chip.
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{{cache info
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|l1i cache=32 KB
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|l1i break=1x32 KB
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|l1i desc=2-way set associative
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|l1i extra=
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|l1d cache=32 KB
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|l1d break=1x32 KB
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|l1d desc=2-way set associative
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|l1d extra=
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|l2 cache=
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|l2 break=
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|l2 desc=
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|l2 extra=
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|l3 cache=
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|l3 break=
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|l3 desc=
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|l3 extra=
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}}
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== Graphics ==
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This SoC has no integrated graphics processing unit.
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== Features ==
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{{mpu features
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| mmx  = true
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| 3dnow = true
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}}
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* Auto-power down state
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* Stop clock state

Revision as of 22:43, 3 August 2016

Template:mpu K6-2/500AFX was a 32-bit x86 K6-2-based microprocessor designed and manufactured in 1999 by AMD. Manufactured using a 0.25 µm process, this MPU operated at 500 MHz with a FSB of 100 MHz consumed 20.7 W.

Cache

Main article: K6-2 § Cache

L2$ can be 512 KB to 2 MB, depending on manufacturer and motherboard model. L2$ is off-chip.

Cache Info [Edit Values]
L1I$ 32 KB
"KB" is not declared as a valid unit of measurement for this property.
1x32 KB 2-way set associative
L1D$ 32 KB
"KB" is not declared as a valid unit of measurement for this property.
1x32 KB 2-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Auto-power down state
  • Stop clock state
Facts about "K6-2/500AFX - AMD"
l1d$ description2-way set associative +
l1i$ description2-way set associative +