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|model number=7232P
 
|model number=7232P
 
|part number=100-000000081
 
|part number=100-000000081
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|part number 2=100-100000081WOF
 
 
|market=Server
 
|market=Server
 
|first announced=August 7, 2019
 
|first announced=August 7, 2019
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|frequency=3,100 MHz
 
|frequency=3,100 MHz
 
|turbo frequency=3,200 MHz
 
|turbo frequency=3,200 MHz
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|clock multiplier=31
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|clock multiplier=28
 
|isa=x86-64
 
|isa=x86-64
 
|isa family=x86
 
|isa family=x86
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|core name=Rome
 
|core name=Rome
 
|core family=23
 
|core family=23
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|core model=49
 
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|core stepping=B0
 
 
|process=7 nm
 
|process=7 nm
 
|process 2=14 nm
 
|process 2=14 nm
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|package name 1=amd,socket_sp3
 
|package name 1=amd,socket_sp3
 
}}
 
}}
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'''EPYC 7232P''' is a {{arch|64}} [[octa-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7232P has a TDP of 120 W with a base frequency of 3.1 GHz and a {{amd|precision boost|boost}} frequency of up to 3.2 GHz. This processor supports single-socket configurations only and up to 4 TiB of memory per socket.
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'''EPYC 7232P''' is a {{arch|64}} [[octa-core]] [[x86]] server microprocessor designed and introduced by [[AMD]] in mid-[[2019]]. This [[multi-chip package|multi-chip processor]], which is based on the {{amd|Zen 2|Zen 2 microarchitecture|l=arch}}, incorporates logic fabricated [[TSMC]] [[7 nm process]] and I/O fabricated on [[GlobalFoundries]] [[14 nm process]]. The 7232P has a TDP of 120 W with a base frequency of 3.1 GHz and a {{amd|precision boost|boost}} frequency of up to 3.2 GHz. This processor supports single-socket configurations only and up to 4 TiB of eight channels DDR4-3200 memory per socket.
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This processor has 8 CPU cores and 32 MiB L3 cache. A single Core Complex Die (plus I/O die) can provide these resources, however there seems to be no evidence that AMD produces any Zen 2-based EPYC or Threadripper processors with an odd number of CCDs, and the advertised maximum memory bandwidth appears to exceed the capabilities of a single CCD. The [[EPYC 7252]] SKU notably has the same specifications as this model except for supporting dual-socket systems and offering 64 MiB L3 cache which evidently requires two CCDs.
 
  
 
== Cache ==
 
== Cache ==
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|l1d break=8x32 KiB
 
|l1d break=8x32 KiB
 
|l1d desc=8-way set associative
 
|l1d desc=8-way set associative
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|l1d policy=write-back
 
 
|l2 cache=4 MiB
 
|l2 cache=4 MiB
 
|l2 break=8x512 KiB
 
|l2 break=8x512 KiB
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== Memory controller ==
 
== Memory controller ==
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This model supports up to 8 channels of up to DDR4-3200 memory<ref name="specs">[https://www.amd.com/en/products/cpu/amd-epyc-7232p "AMD EPYC™ 7232P"]. <i>AMD.com</i>. Retrieved October 2020.</ref><ref name="datasheet">[https://www.amd.com/system/files/documents/AMD-EPYC-7002-Series-Datasheet.pdf "AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter"], AMD Publ. #LE-70002, Rev. 02, April 2020</ref> with a theoretical maximum bandwidth of 25.6 GB/s (≈ 23.84 GiB/s) per channel, but is apparently bandwidth limited by the [[amd/infinity_fabric|IFOP]] links between the I/O die and its only one (two?) compute dies (effective bandwidth ≈ 55 GB/s per CCD at 1.46 GHz FCLK<ref name="isscc2020j-chiplet">Naffziger, Samuel; Lepak, Kevin; Paraschou, Milam; Subramony, Mahesh (2020). <i>2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products</i>. 2020 IEEE International Solid-State Circuits Conference. pp. 44-45. doi:[https://doi.org/10.1109/ISSCC19947.2020.9063103 10.1109/ISSCC19947.2020.9063103]</ref>). According to AMD this processor is "optimized for 4 channels with DDR4-2667 DIMMs" (≈ 21.3 GB/s per channel) and therefore has a "per-socket theoretical memory bandwidth 85.3 GB/s" (≈ 79.47 GiB/s).<ref name="datasheet"/>
 
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{{memory controller
 
{{memory controller
 
|type=DDR4-3200
 
|type=DDR4-3200
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}}
 
}}
  
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== Features ==
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== Features ==  
 
{{x86 features
 
{{x86 features
 
|real=Yes
 
|real=Yes
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|amdpbod=No
 
|amdpbod=No
 
}}
 
}}
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== References ==
 
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<references/>
 

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Retrieved from "https://en.wikichip.org/wiki/amd/epyc/7232p"
Facts about "EPYC 7232P - AMD"
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Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
EPYC 7232P - AMD#pcie +
base frequency3,100 MHz (3.1 GHz, 3,100,000 kHz) +
clock multiplier31 +
core count8 +
core family23 +
core model49 +
core nameRome +
core steppingB0 +
designerAMD +
die count2 +
familyEPYC +
first announcedAugust 7, 2019 +
first launchedAugust 7, 2019 +
full page nameamd/epyc/7232p +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd precision boost 2true +
has amd secure encrypted virtualization technologytrue +
has amd secure memory encryption technologytrue +
has amd sensemi technologytrue +
has amd transparent secure memory encryption technologytrue +
has ecc memory supporttrue +
has featureAdvanced Encryption Standard Instruction Set Extension +, Advanced Vector Extensions +, Advanced Vector Extensions 2 +, Precision Boost 2 + and SenseMI Technology +
has locked clock multipliertrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size512 KiB (524,288 B, 0.5 MiB) +
l1d$ description8-way set associative +
l1d$ size256 KiB (262,144 B, 0.25 MiB) +
l1i$ description8-way set associative +
l1i$ size256 KiB (262,144 B, 0.25 MiB) +
l2$ description8-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldateAugust 7, 2019 +
manufacturerGlobalFoundries + and TSMC +
market segmentServer +
max cpu count1 +
max memory4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) +
max memory bandwidth190.7 GiB/s (195,276.8 MiB/s, 204.763 GB/s, 204,762.566 MB/s, 0.186 TiB/s, 0.205 TB/s) +
max memory channels8 +
microarchitectureZen 2 +
model number7232P +
nameEPYC 7232P +
packageFCLGA-4094 + and SP3 +
part number100-000000081 + and 100-100000081WOF +
process7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 450.00 (€ 405.00, £ 364.50, ¥ 46,498.50) +
series7002 +
smp max ways1 +
socketLGA-4094 + and SP3 +
supported memory typeDDR4-3200 +
tdp120 W (120,000 mW, 0.161 hp, 0.12 kW) +
technologyCMOS +
thread count16 +
turbo frequency3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +