From WikiChip
Difference between revisions of "amd/duron/d950aut1b"
< amd‎ | duron

(Cache)
Line 84: Line 84:
 
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
 
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
 
{{cache info
 
{{cache info
|l1i cache=64 KB
+
|l1i cache=64 KiB
|l1i break=1x64 KB
+
|l1i break=1x64 KiB
 
|l1i desc=2-way set associative
 
|l1i desc=2-way set associative
 
|l1i extra=
 
|l1i extra=
|l1d cache=64 KB
+
|l1d cache=64 KiB
|l1d break=1x64 KB
+
|l1d break=1x64 KiB
 
|l1d desc=2-way set associative
 
|l1d desc=2-way set associative
 
|l1d extra=
 
|l1d extra=
|l2 cache=64 KB
+
|l2 cache=64 KiB
|l2 break=1x64 KB
+
|l2 break=1x64 KiB
 
|l2 desc=16-way set associative
 
|l2 desc=16-way set associative
 
|l2 extra=
 
|l2 extra=

Revision as of 23:48, 20 September 2016

Template:mpu Duron 950 based on the Spitfire core was a 32-bit x86 microprocessor developed by AMD and introduced in 2001. This model was part of the first series of the Duron family. Designed based on AMD's K7 (a Thunderbird-derivative) on a 180 nm process, this MPU operated at 950 MHz with a bus capable of 200 MT/s with a TDP of 41.5 W.

Cache

Main article: K7 § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L1D$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L2$ 64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
1x64 KiB 16-way set associative

Graphics

This SoC has no integrated graphics processing unit.

Features

Template:mpu features

  • Halt State
  • Sleep State
has featureHalt State + and Sleep State +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +