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Difference between revisions of "amd/cpuid"
(Removing cruft from previous.) |
(Fixing my previous addition, for obvious derp reasons, cpuid reported confusing model / ext model, so marking with ??) |
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| {{amd|Zen 2|l=arch}} || {{amd|Rome|l=arch}} (?) || 0x8 || 0xF || 0x2 || 0x? || Family 23 Model [32-47] | | {{amd|Zen 2|l=arch}} || {{amd|Rome|l=arch}} (?) || 0x8 || 0xF || 0x2 || 0x? || Family 23 Model [32-47] | ||
|- | |- | ||
| − | | rowspan="2" | {{amd|Zen+|l=arch}} || {{amd|Picasso|l=core}} || 0x8 || 0xF || | + | | rowspan="2" | {{amd|Zen+|l=arch}} || {{amd|Picasso|l=core}} || 0x8 || 0xF || 0x1?? || 0x8 || [[Family 23 Model 24]] |
|- | |- | ||
| {{amd|Pinnacle Ridge|l=core}} || 0x8 || 0xF || 0x0 || 0x8 || [[Family 23 Model 8]] | | {{amd|Pinnacle Ridge|l=core}} || 0x8 || 0xF || 0x0 || 0x8 || [[Family 23 Model 8]] | ||
Revision as of 04:17, 30 April 2019
x86
Instruction Set Architecture
Instruction Set Architecture
General
Variants
Topics
- Instructions
- Addressing Modes
- Registers
- Model-Specific Register
- Assembly
- Interrupts
- Micro-Ops
- Timer
- Calling Convention
- Microarchitectures
- CPUID
CPUIDs
- AMD's CPUIDs
- Intel's CPUIDs
Modes
Extensions(all)
Below is a list of AMD's CPUID broken down by their respective core names and microarchitecture:
This article is a work in progress!CPUIDs
Family 23
| Microarchitecture | Core | Extended Family | Family | Extended Model | Model | |
|---|---|---|---|---|---|---|
| Zen 3 | ||||||
| Zen 2 | Rome (?) | 0x8 | 0xF | 0x2 | 0x? | Family 23 Model [32-47] |
| Zen+ | Picasso | 0x8 | 0xF | 0x1?? | 0x8 | Family 23 Model 24 |
| Pinnacle Ridge | 0x8 | 0xF | 0x0 | 0x8 | Family 23 Model 8 | |
| Zen | Raven Ridge | 0x8 | 0xF | 0x1 | 0x1 | Family 23 Model 17 |
| Naples, Whitehaven, Summit Ridge, Snowy Owl | 0x8 | 0xF | 0x0 | 0x1 | Family 23 Model 1 |
