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Information for "amd/cores/rome"
Basic information
Display title | Rome - Cores - AMD |
Default sort key | Rome, AMD |
Page length (in bytes) | 6,333 |
Page ID | 18127 |
Page content language | English (en) |
Page content model | wikitext |
Indexing by robots | Allowed |
Number of redirects to this page | 1 |
Counted as a content page | Yes |
Number of subpages of this page | 0 (0 redirects; 0 non-redirects) |
Page protection
Edit | Allow all users (infinite) |
Move | Allow all users (infinite) |
Edit history
Page creator | Inject (talk | contribs) |
Date of page creation | 19:26, 16 May 2017 |
Latest editor | David (talk | contribs) |
Date of latest edit | 16:47, 15 April 2020 |
Total number of edits | 38 |
Total number of distinct authors | 8 |
Recent number of edits (within past 90 days) | 0 |
Recent number of distinct authors | 0 |
Page properties
Transcluded templates (20) | Templates used on this page:
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Facts about "Rome - Cores - AMD"
back image | ![]() |
designer | AMD + |
first announced | May 16, 2017 + |
first launched | August 7, 2019 + |
instance of | core + |
isa | x86-64 + |
isa family | x86 + |
main image | ![]() |
main image caption | Package front + |
manufacturer | TSMC + and GlobalFoundries + |
microarchitecture | Zen 2 + |
name | Rome + |
package | FCLGA-4094 + and SP3 + |
process | 7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) + |
socket | LGA-4094 + and SP3 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |