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Latest revision | Your text | ||
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* 60 PCIe lanes | * 60 PCIe lanes | ||
* Quad-channel Memory | * Quad-channel Memory | ||
− | ** Up to DDR4- | + | ** Up to DDR4-2666 ECC |
** Up to 1 [[TiB]] | ** Up to 1 [[TiB]] | ||
* Up to 32 cores / 64 threads | * Up to 32 cores / 64 threads |
Facts about "Colfax - Cores - AMD"
designer | AMD + |
first announced | August 6, 2018 + |
first launched | August 13, 2018 + |
instance of | core + |
isa | x86-64 + |
manufacturer | GlobalFoundries + |
microarchitecture | Zen+ + |
name | Colfax + |
package | FCLGA-4094 + and TR4 + |
process | 12 nm (0.012 μm, 1.2e-5 mm) + |
socket | TR4 +, SP3r2 + and sTR4 + |
technology | CMOS + |
word size | 64 bit (8 octets, 16 nibbles) + |