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Chagall - Cores - AMD
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Chagall
General Info
DesignerAMD
ManufacturerTSMC, GlobalFoundries
IntroductionMarch 8, 2022 (launched)
Microarchitecture
ISAx86-64
MicroarchitectureZen 3
Word Size
8 octets
16 nibbles
64 bit
Process7 nm
0.007 μm
7.0e-6 mm
TechnologyCMOS
Packaging
PackagesWRX8 (FC-OLGA)
Dimension75.40 mm × 58.50 mm × 6.26 mm
Pitch0.87 mm × 1.00 mm
Pin Count4094
SocketSocket sWRX8
Succession

Chagall is the codename of AMD's fourth generation Ryzen Threadripper HEDT and workstation processors based on the Zen 3 microarchitecture. They succeeded the third generation Ryzen Threadripper 3900 "Castle Peak" series.

On March 8, 2022 AMD introduced the Ryzen Threadripper PRO 5900 WX-Series. These are workstation processors available only in tray packaging to OEMs. They identify as members of AMD x86 CPU Family 19h, Model 08h.

Overview[edit]

"Chagall" is a SoC derived from the EPYC 7003 "Milan" server processor series. Accordingly these are multi-chip processors integrating a large I/O die fabricated on a GlobalFoundries 12 nm (14 nm?) process and up to eight Core Complex Dies fabricated on a TSMC advanced 7 nm process. They support 2-way multithreading with up to 64 cores and 128 threads per processor. Multiprocessing is not supported.

Workstation versions use the Socket sWRX8 infrastructure which supports up to eight DDR4 memory channels with a maximum of one DIMM per channel, either UDIMMs or RDIMMs, eight 16-lane PCIe Gen 4 I/O links, four USB 3.2 Gen 2 ports, and up to 32 SATA Gen 3 ports.

HEDT versions have not been released as of March 2022, they are bound to use Socket sTRX4.

Input/Output Interfaces[edit]

"Chagall" processors integrate eight PCIe controllers and four SATA controllers. They have eight 16-lane PCIe Gen 1, 2, 3, 4 (16 GT/s) interfaces, each configurable as up to eight x16/x8/x4/x2/x1 wide (e.g. 1x4 + 4x1 + 1x8) links, so 128 lanes total. Some of these lanes are configurable as SATA Gen 1, 2, 3 (6 Gb/s) link. Up to 32 SATA ports are available from the processor in total, as well as four USB 3.2 Gen 2×1 (10 Gb/s) ports, and various low speed interfaces. For details see Socket sWRX8.

On Socket sWRX8 motherboards the PCIe interfaces are generally used for x16 PCIe slots and x4 M.2 NVMe/SATA SSD connectors, leveraging few of the CPU's SATA ports. One x8 PCIe link on the processor is reserved to attach the AMD WRX80 chipset which serves as I/O expander, a member of the AMD-500 Series with I/O capabilities similar to the TRX40 and X570 chipsets for Socket sTRX4 and AM4 processors: 16 lanes (plus 8-lane CPU link) PCIe Gen 1, 2, 3, 4; 12 SATA Gen 1, 2, 3 ports, eight sharing pins with the PCIe interface and four dedicated; eight USB 3.2 Gen 2 (10 Gb/s) ports, and five USB 2.0 ports. The chipset PCIe interfaces are generally used for PCIe slots, on-board Ethernet controllers, M.2 SSD and WLAN connectors. An audio interface is not provided by the processor or the chipset, an audio controller is commonly attached as on-board USB device. The sWRX8/WRX80 platform does not support overclocking.

Feature Summary[edit]

"Chagall" processors released as of March 2022 have the following features:

  • 8 × 64/72 bit DDR4 SDRAM interface
    • Up to 1600 MHz, PC4-25600 (DDR4-3200), 204.8 GB/s total raw bandwidth
    • One DIMM per channel, up to 8 DIMMs total
    • SR/DR UDIMM, RDIMM, LRDIMM, or 3DS RDIMM types
    • ECC supported
    • Max. total memory capacity 2 TiB using eight 256 GiB LRDIMMs or 3DS DIMMs
  • Eight 16-lane PCIe Gen 1, 2, 3, 4 (16 GT/s) controllers and interfaces
    • Up to 8 ports per interface configurable x16, x8, x4, x2, x1 (e.g. 1x4 + 4x1 + 1x8)
    • Up to 120 PCIe lanes total (one x8 link reserved to attach the chipset)
  • Four SATA Gen 1, 2, 3 (6 Gb/s) controllers
    • Alternative function of certain PCIe lanes
    • Up to 32 SATA ports total
  • 4 × USB 1.1, 2.0, 3.2 Gen 2×1 (10 Gb/s) ports from two XHCI USB controllers
    • Type-C connectors are supported with external components

Chagall Processors[edit]

ModelFamilyMicroarch.CoresThreadsL2$L3$BaseTurboMemoryTDPSocketLaunchedOPN
PRO 5945WXRyzen ThreadripperZen 312246 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
4.1 GHz
4,100 MHz
4,100,000 kHz
4.5 GHz
4,500 MHz
4,500,000 kHz
DDR4-3200280 W
280,000 mW
0.375 hp
0.28 kW
sWRX88 March 2022100-000000448
PRO 5955WXRyzen ThreadripperZen 316328 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
64 MiB
65,536 KiB
67,108,864 B
0.0625 GiB
4 GHz
4,000 MHz
4,000,000 kHz
4.5 GHz
4,500 MHz
4,500,000 kHz
DDR4-3200280 W
280,000 mW
0.375 hp
0.28 kW
sWRX88 March 2022100-000000447
PRO 5965WXRyzen ThreadripperZen 3244812 MiB
12,288 KiB
12,582,912 B
0.0117 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
3.8 GHz
3,800 MHz
3,800,000 kHz
4.5 GHz
4,500 MHz
4,500,000 kHz
DDR4-3200280 W
280,000 mW
0.375 hp
0.28 kW
sWRX88 March 2022100-000000446
PRO 5975WXRyzen ThreadripperZen 3326416 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
128 MiB
131,072 KiB
134,217,728 B
0.125 GiB
3.6 GHz
3,600 MHz
3,600,000 kHz
4.5 GHz
4,500 MHz
4,500,000 kHz
DDR4-3200280 W
280,000 mW
0.375 hp
0.28 kW
sWRX88 March 2022100-000000445
PRO 5995WXRyzen ThreadripperZen 36412832 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
256 MiB
262,144 KiB
268,435,456 B
0.25 GiB
2.7 GHz
2,700 MHz
2,700,000 kHz
4.5 GHz
4,500 MHz
4,500,000 kHz
DDR4-3200280 W
280,000 mW
0.375 hp
0.28 kW
sWRX88 March 2022100-000000444
Count: 5

Bibliography[edit]

See also[edit]

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Facts about "Chagall - Cores - AMD"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
Chagall - Cores - AMD#package +
designerAMD +
first launchedMarch 8, 2022 +
instance ofcore +
isax86-64 +
manufacturerTSMC + and GlobalFoundries +
microarchitectureZen 3 +
nameChagall +
packagesWRX8 +
process7 nm (0.007 μm, 7.0e-6 mm) +
socketSocket sWRX8 +
technologyCMOS +
word size64 bit (8 octets, 16 nibbles) +