From WikiChip
Difference between revisions of "amd/athlon mp/amsn2600dkt3c"
< amd‎ | athlon mp

(Features)
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| e3dnow      = Yes
 
| e3dnow      = Yes
 
| sse        = Yes
 
| sse        = Yes
 +
| amd smartmp = Yes
 
}}
 
}}
 
* Advanced Configuration and Power Interface [[has feature::ACPI| ]]
 
* Advanced Configuration and Power Interface [[has feature::ACPI| ]]

Revision as of 12:07, 17 November 2016

Template:mpu The Athlon MP 2600+ (OPN AMSN2600DKT3C) based on the Thoroughbred core was a 32-bit x86 multiprocessor developed by AMD and introduced in late 2002 for the server and workstation market. This MPU operated at 2.1 GHz with a FSB transfer rate of 266 MT/s (x16 multiplier), was manufactured on a newer 130 nm process.

Cache

Main article: K7 § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L1D$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L2$ 256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
1x256 KiB 16-way set associative

Graphics

This MPU has no integrated graphics processing unit.

Features

Template:mpu features

  • Advanced Configuration and Power Interface
    • Halt State
    • Stop Grant State

Documents

Datasheets

Others

Facts about "Athlon MP 2600+ - AMD"
has featureACPI +, Halt State + and Stop Grant State +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +