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Athlon MP 2100+ - AMD
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Template:mpu The Athlon MP 2100+ (OPN AMP2100DMS3C) based on the Palomino core was a 32-bit x86 multiprocessor developed by AMD and introduced in mid-2002 for the server and workstation market. This MPU operated at 1.73 GHz with a FSB transfer rate of 266 MT/s (x13 multiplier). This processor, which was based on the K7 microarchitecture, was manufactured on a mature 180 nm copper interconnect technology at AMD's Fab 30 in Dresden, Germany.

Cache

Main article: K7 § Cache

[Edit/Modify Cache Info]

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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$128 KiB
131,072 B
0.125 MiB
L1I$64 KiB
65,536 B
0.0625 MiB
1x64 KiB2-way set associative 
L1D$64 KiB
65,536 B
0.0625 MiB
1x64 KiB2-way set associative 

L2$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
  1x256 KiB16-way set associative 

Graphics

This MPU has no integrated graphics processing unit.

Features

[Edit/Modify Supported Features]

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Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
3DNow!3DNow! Extension
E3DNow!Extended 3DNow! Extension
SSEStreaming SIMD Extensions
x86-1616-bit x86
x86-3232-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
SmartMPSmartMP Technology
  • Advanced Configuration and Power Interface
    • Halt State
    • Stop Grant State

Documents

Datasheets

Others

Facts about "Athlon MP 2100+ - AMD"
has amd smartmp technologytrue +
has featureSmartMP Technology +, ACPI +, Halt State + and Stop Grant State +
has multiprocessing supporttrue +
l1$ size128 KiB (131,072 B, 0.125 MiB) +
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +