Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "amd/athlon mp/amp2100dms3c"
| Line 72: | Line 72: | ||
| socket 0 type = PGA-462 | | socket 0 type = PGA-462 | ||
}} | }} | ||
| − | The '''Athlon MP 2100+''' (OPN ''AMP2100DMS3C'') based on the {{amd|Palomino|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2001]] for the server and workstation market. This MPU operated at 1.73 GHz with a FSB transfer rate of 266 MT/s (x13 multiplier). | + | The '''Athlon MP 2100+''' (OPN ''AMP2100DMS3C'') based on the {{amd|Palomino|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in late [[2001]] for the server and workstation market. This MPU operated at 1.73 GHz with a FSB transfer rate of 266 MT/s (x13 multiplier). This processor, which was based on the {{amd|K7|K7 microarchitecture|l=arch}}, was manufactured on a mature [[180 nm]] copper interconnect technology at AMD's Fab 30 in Dresden, Germany. |
Revision as of 01:18, 17 November 2016
Template:mpu The Athlon MP 2100+ (OPN AMP2100DMS3C) based on the Palomino core was a 32-bit x86 multiprocessor developed by AMD and introduced in late 2001 for the server and workstation market. This MPU operated at 1.73 GHz with a FSB transfer rate of 266 MT/s (x13 multiplier). This processor, which was based on the K7 microarchitecture, was manufactured on a mature 180 nm copper interconnect technology at AMD's Fab 30 in Dresden, Germany.
