From WikiChip
Difference between revisions of "amd/athlon mp/ahx1000ams3c"
< amd‎ | athlon mp

(+cache)
Line 73: Line 73:
 
}}
 
}}
 
'''Athlon MP 1000''' (OPN ''AHX1000AMS3C'') based on the {{amd|Palomino|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in [[2001]] for the server and workstation market. The MP 1000 was AMD's first dual-socket microprocessor (along with the {{\\|AHX1200AMS3C|1200}}). This model operated at 1 GHz with a FSB transfer rate of 266 MT/s with a typical TDP of 41.3 W. This processor, which was based on the {{amd|K7|K7 microarchitecture|l=arch}}, was manufactured on a mature [[180 nm]] copper interconnect technology at AMD's Fab 30 in Dresden, Germany.
 
'''Athlon MP 1000''' (OPN ''AHX1000AMS3C'') based on the {{amd|Palomino|l=core}} core was a {{arch|32}} [[x86]] [[multiprocessor]] developed by [[AMD]] and introduced in [[2001]] for the server and workstation market. The MP 1000 was AMD's first dual-socket microprocessor (along with the {{\\|AHX1200AMS3C|1200}}). This model operated at 1 GHz with a FSB transfer rate of 266 MT/s with a typical TDP of 41.3 W. This processor, which was based on the {{amd|K7|K7 microarchitecture|l=arch}}, was manufactured on a mature [[180 nm]] copper interconnect technology at AMD's Fab 30 in Dresden, Germany.
 +
 +
== Cache ==
 +
{{main|amd/microarchitectures/k7#Memory_Hierarchy|l1=K7 § Cache}}
 +
{{cache info
 +
|l1i cache=64 KiB
 +
|l1i break=1x64 KiB
 +
|l1i desc=2-way set associative
 +
|l1i extra=
 +
|l1d cache=64 KiB
 +
|l1d break=1x64 KiB
 +
|l1d desc=2-way set associative
 +
|l1d extra=
 +
|l2 cache=64 KiB
 +
|l2 break=1x64 KiB
 +
|l2 desc=16-way set associative
 +
|l2 extra=
 +
|l3 cache=
 +
|l3 break=
 +
|l3 desc=
 +
|l3 extra=
 +
}}

Revision as of 01:29, 17 November 2016

Template:mpu Athlon MP 1000 (OPN AHX1000AMS3C) based on the Palomino core was a 32-bit x86 multiprocessor developed by AMD and introduced in 2001 for the server and workstation market. The MP 1000 was AMD's first dual-socket microprocessor (along with the 1200). This model operated at 1 GHz with a FSB transfer rate of 266 MT/s with a typical TDP of 41.3 W. This processor, which was based on the K7 microarchitecture, was manufactured on a mature 180 nm copper interconnect technology at AMD's Fab 30 in Dresden, Germany.

Cache

Main article: K7 § Cache
Cache Info [Edit Values]
L1I$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L1D$ 64 KiB
65,536 B
0.0625 MiB
1x64 KiB 2-way set associative
L2$ 64 KiB
0.0625 MiB
65,536 B
6.103516e-5 GiB
1x64 KiB 16-way set associative
Retrieved from "https://en.wikichip.org/w/index.php?title=amd/athlon_mp/ahx1000ams3c&oldid=27692"
Facts about "Athlon MP 1000 - AMD"
RDF feed
l1d$ description2-way set associative +
l1d$ size64 KiB (65,536 B, 0.0625 MiB) +
l1i$ description2-way set associative +
l1i$ size64 KiB (65,536 B, 0.0625 MiB) +
l2$ description16-way set associative +
l2$ size0.0625 MiB (64 KiB, 65,536 B, 6.103516e-5 GiB) +