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Difference between revisions of "amd/am486/am486dx2-66v16b"
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| market = Desktop | | market = Desktop | ||
| first announced = | | first announced = | ||
− | | first launched = | + | | first launched = 1997 |
| last order = | | last order = | ||
| last shipment = | | last shipment = | ||
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| socket 3 = Socket 3 | | socket 3 = Socket 3 | ||
}} | }} | ||
− | '''Am486DX2-66V16B''' was an {{ | + | '''Am486DX2-66V16B''' was an Enhanced {{amd|Am486}} microprocessor introduced by [[AMD]] in 1997. This processor had a clock multiplier of 2 having base frequency of 100 MHz with a bus frequency of 50 MHz. This model had a write-back cache and double the size of L1 of previous models (16 KB). The {{\\|Am486DX2-66V8T}} is an 8 KB version similar to this model. This "Enhanced" Am486 includes some other features such as SMM. |
== Cache == | == Cache == | ||
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== Graphics == | == Graphics == | ||
This chip had no integrated graphics processing unit. | This chip had no integrated graphics processing unit. | ||
+ | |||
+ | == Features == | ||
+ | * [[has feature::System Management Mode]] (SMM) | ||
== See also == | == See also == | ||
* {{amd|Am486|Am486 family}} | * {{amd|Am486|Am486 family}} |
Revision as of 22:39, 15 May 2016
Template:mpu Am486DX2-66V16B was an Enhanced Am486 microprocessor introduced by AMD in 1997. This processor had a clock multiplier of 2 having base frequency of 100 MHz with a bus frequency of 50 MHz. This model had a write-back cache and double the size of L1 of previous models (16 KB). The Am486DX2-66V8T is an 8 KB version similar to this model. This "Enhanced" Am486 includes some other features such as SMM.
Contents
Cache
- Main article: 80486 § Cache
Cache Info [Edit Values] | ||
L1$ | 16 KB "KB" is not declared as a valid unit of measurement for this property. |
1x16 KB 4-way set associative (unified, write-back policy) |
Graphics
This chip had no integrated graphics processing unit.
Features
- System Management Mode (SMM)
See also
Facts about "Am486DX2-66V16B - AMD"
has feature | System Management Mode + |
l1$ description | 4-way set associative + |