From WikiChip
Difference between revisions of "amd/am486/am486dx2-50"
< amd‎ | am486

Line 64: Line 64:
  
 
| packaging          = Yes
 
| packaging          = Yes
| package             = PGA-168
+
| package 0          = CPGA-168
| package type       = PGA
+
| package 0 type     = CPGA
| package pitch       =  
+
| package 0 pins      = 168
| package size        =  
+
| package 0 pitch     = 2.286 mm
| socket             = Socket 1
+
| package 0 width    = 44.069 mm
| socket 2           = Socket 2
+
| package 0 length    = 44.069 mm
| socket 3           = Socket 3
+
| package 0 height    = 3.556 mm
 +
| socket 0            = Socket 1
 +
| socket 0 type      =
 +
| socket 0 2         = Socket 2
 +
| socket 0 2 type    =
 +
| socket 0 3         = Socket 3
 +
| socket 0 3 type    =
 
}}
 
}}
 
'''Am486DX2-50''' was an {{intel|80486}}-compatible microprocessor introduced by [[AMD]] in 1993. This processor had a clock multiplier of 2 having base frequency of 50 MHz with a FSB frequency of 25 MHz.
 
'''Am486DX2-50''' was an {{intel|80486}}-compatible microprocessor introduced by [[AMD]] in 1993. This processor had a clock multiplier of 2 having base frequency of 50 MHz with a FSB frequency of 25 MHz.

Revision as of 22:37, 16 May 2016

Template:mpu Am486DX2-50 was an 80486-compatible microprocessor introduced by AMD in 1993. This processor had a clock multiplier of 2 having base frequency of 50 MHz with a FSB frequency of 25 MHz.

Cache

Main article: 80486 § Cache
Cache Info [Edit Values]
L1$ 8 KB
"KB" is not declared as a valid unit of measurement for this property.
1x8 KB 4-way set associative (unified, write-through policy)

Graphics

This chip had no integrated graphics processing unit.

See also

Facts about "Am486DX2-50 - AMD"
l1$ description4-way set associative +