Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "amd/am186/n80c186-25"
(→Cache) |
m (Bot: corrected mem) |
||
| Line 41: | Line 41: | ||
| core count = 1 | | core count = 1 | ||
| max cpus = 1 | | max cpus = 1 | ||
| − | | max memory = 1 | + | | max memory = 1 MiB |
| max memory addr = | | max memory addr = | ||
Revision as of 04:01, 23 June 2017
Template:mpu N80C186-25 is an 80186-based microprocessor manufactured by AMD. This model is a redesigned CMOS version that operated at 25 MHz and introduced a number of enhancements in addition to being lower-power CMOS, including a DRAM Refresh Control Unit and various power saving modes.
Contents
Cache
- Main article: 80186 § Cache
| Cache Info [Edit Values] | ||
| L1$ | 0 KiB 0 B 0 MiB |
1x0 KiB |
| L2$ | 0 KiB 0 MiB 0 B 0 GiB |
1x0 KiB |
Graphics
This chip had no integrated graphics processing unit.
Features
- 10 new instructions
- Two DMA channels
- Three programmable interrupt timers
- Local Bus Controller
- Object code-compatible with all 86/88 software
- Power saving mode
- DRAM Refresh Control Unit
Documents
- AMD 80C186 (June 1994), Publication #17907 Rev B
