From WikiChip
Package SP4 - AMD
< amd
Revision as of 06:09, 6 April 2022 by QuietRub (talk | contribs) (Created page with "{{amd title|Package SP4}} {{package |name=SP4 |designer=AMD |market=Embedded |first launched=February 21, 2018 |microarch=Zen |tdp=55 W |tdp 2=100 W |package name=SP4 |package...")
(diff) ← Older revision | Latest revision (diff) | Newer revision → (diff)

Edit Values
SP4
General Info
DesignerAMD
IntroductionFebruary 21, 2018 (launched)
MarketEmbedded
MicroarchitectureZen
TDP55 W, 100 W
Package
NameSP4
TypeFC-OBGA
Dimension45 mm × 45 mm
Pitch0.8 mm

SP4 and SP4r2 are microprocessor packages of AMD EPYC 3000 "Snowy Owl" embedded processors. Server processors of the same generation (EPYC 7001) use Socket SP3.

Overview[edit]

SP4 and SP4r2 are ball grid array packages with 0.8 mm non-uniform pitch, 45 mm × 45 mm in size, with flip chip die attachment and a stiffener frame. The processors using these packages are members of AMD's x86 CPU Family 17h with CPU cores based on the Zen microarchitecture, and are fabricated on a GlobalFoundries 14 nm process.

SP4 is a multi-chip package with two identical "Zeppelin" ZP-B2 dies. AMD used the same dies in various revisions for EPYC 7001 server and embedded processors, first generation Ryzen Threadripper HEDT and Ryzen desktop processors; see CPU Family 17h. The pin compatible SP4r2 package carries one of these dies. They integrate eight CPU cores, two memory controllers, two 16-lane multi-function I/O interfaces and other I/O facilities. Both package types are intended for single processor systems so xGMI links are not supported. As on Ryzen Threadripper 1900 processors two GMI links connect the dies of the SP4 package. The multi-function I/O interfaces can be configured as PCIe, SATA, SATA Express, or XGBE links. The latter support the 10GBASE-KR, 1000BASE-KX, and SGMII (10/100/1000 Mbit/s) backplane Ethernet protocols.

Features[edit]

  • Lidless ball grid array package with stiffener frame, 45 mm × 45 mm
    •  ? contacts, 0.8 mm non-uniform pitch
    • Organic substrate, flip chip die attachment
  • 4 × 72 bit DDR4 SDRAM interface (SP4)
  • 2 × 72 bit DDR4 SDRAM interface (SP4r2)
    • Up to 1333 MHz, PC4-21333 (DDR4-2666), 85.33 GB/s total raw bandwidth (SP4)
    • Up to 2 DIMMs/channel
    • SR/DR UDIMM, SR/DR SODIMM, SR/DR RDIMM, 4R/8R LRDIMM, 3DS DIMM, NVDIMM-N types
    • ECC support
    • Memory addressing up to ? GiB/channel
    • Max. total memory capacity 1 TiB using 8 × 128 GiB LRDIMMs (SP4)
  • Four multi-function I/O interfaces P0, P1, G0, G1 (SP4)
  • Two multi-function I/O interfaces P0, G0 (SP4r2)
Lane 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
PCIe x16
x8 x8
x4 x4 x4 x4
x2 x2 x2 x2 x2 x2 x2 x2
x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1 x1
SATAe 1 0
SATA 7 6 5 4 3 2 1 0
XGBE 3 2 1 0
PHY 4 PHY 3 PHY 2 PHY 1 PHY 0
  • PCIe Gen 1, 2, 3 (8 GT/s) protocol supported on all interfaces
    • 16 lanes, up to 8 ports per interface configurable x16, x8, x4, x2, x1 with power-of-two alignment (e.g. 1x4 + 4x1 + 1x8)
    • Max. 7 PCIe ports in each 8-lane subset (e.g. 0x8 + 8x1 is not possible)
    • Max. 7 PCIe ports per interface if any lane is configured as SATA port
    • Different PCIe generations supported on the ports in the same interface
    • Lane polarity inversion, per port lane reversal
    • Up to 64 (SP4) or 32 (SP4r2) PCIe lanes total
  • SATA Express supported on the lowest four lanes of P0 and G1
    • Combines PCIe and SATA controllers on the same two lanes with a GPIO pin for a device to indicate its controller type
    • P0: SATAE00, SATAE01; G1: SATAE10, SATAE11
    • Up to 4 (SP4) or 2 (SP4r2) ports total
  • SATA Gen 1, 2, 3 (6 Gb/s) protocol supported on the lower 8 lanes of P0 and G1
    • P0: SATA00-07, G1: SATA10-17
    • Up to 16 (SP4) or 8 (SP4r2) ports total
  • XGBE protocols supported on lanes 4-7 of P0 and G1
    • P0: XGBE00-03, G1: XGBE10-13
    • Up to 8 (SP4) or 4 (SP4r2) ports total
  • Five PHY groups on each interface
    • Lanes sharing a PHY group must use the same protocol (PCIe, SATA, XGBE)
  • 4 × USB 1.1, 2.0, 3.1 Gen 1 (5 Gb/s) ports

Processors using package SP4/SP4r2[edit]

ModelCoresThreadsL2$L3$Base
Frequ.
Turbo
one core
Memory
(1DPC)
Memory
channels
TjminTjmaxcTDPTDPPackageLaunchedPriceLTBOPN
3101442 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
8 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
2.1 GHz
2,100 MHz
2,100,000 kHz
2.9 GHz
2,900 MHz
2,900,000 kHz
DDR4-266620 °C
273.15 K
32 °F
491.67 °R
95 °C
368.15 K
203 °F
662.67 °R
35 W
35,000 mW
0.0469 hp
0.035 kW
SP4r221 February 20182028PE3101BIR4KAF
3151482 MiB
2,048 KiB
2,097,152 B
0.00195 GiB
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
2.7 GHz
2,700 MHz
2,700,000 kHz
2.9 GHz
2,900 MHz
2,900,000 kHz
DDR4-266620 °C
273.15 K
32 °F
491.67 °R
95 °C
368.15 K
203 °F
662.67 °R
45 W
45,000 mW
0.0603 hp
0.045 kW
SP4r221 February 20182028PE3151BJR48AF
3201884 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
1.5 GHz
1,500 MHz
1,500,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
DDR4-213320 °C
273.15 K
32 °F
491.67 °R
95 °C
368.15 K
203 °F
662.67 °R
30 W
30,000 mW
0.0402 hp
0.03 kW
SP4r221 February 20182028PE3201BHR88AF
32518164 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
2.5 GHz
2,500 MHz
2,500,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
DDR4-266620 °C
273.15 K
32 °F
491.67 °R
105 °C
378.15 K
221 °F
680.67 °R
55 W
55,000 mW
0.0738 hp
0.055 kW
SP4r221 February 2018$ 315.00
€ 283.50
£ 255.15
¥ 32,548.95
2028PE3251BGR88AF
32558164 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
16 MiB
16,384 KiB
16,777,216 B
0.0156 GiB
2.5 GHz
2,500 MHz
2,500,000 kHz
3.1 GHz
3,100 MHz
3,100,000 kHz
DDR4-26662-40 °C
233.15 K
-40 °F
419.67 °R
105 °C
378.15 K
221 °F
680.67 °R
30 W
30,000 mW
0.0402 hp
0.03 kW
55 W
55,000 mW
0.0738 hp
0.055 kW
SP4r22028PE3255BGR88AF
330112126 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
2 GHz
2,000 MHz
2,000,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
DDR4-266640 °C
273.15 K
32 °F
491.67 °R
95 °C
368.15 K
203 °F
662.67 °R
65 W
65,000 mW
0.0872 hp
0.065 kW
SP421 February 2018$ 450.00
€ 405.00
£ 364.50
¥ 46,498.50
335112246 MiB
6,144 KiB
6,291,456 B
0.00586 GiB
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
1.9 GHz
1,900 MHz
1,900,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
DDR4-266640 °C
273.15 K
32 °F
491.67 °R
105 °C
378.15 K
221 °F
680.67 °R
60 W
60,000 mW
0.0805 hp
0.06 kW
80 W
80,000 mW
0.107 hp
0.08 kW
SP421 February 20182028PE3351BNQCAAF
340116168 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
1.85 GHz
1,850 MHz
1,850,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
DDR4-266640 °C
273.15 K
32 °F
491.67 °R
105 °C
378.15 K
221 °F
680.67 °R
85 W
85,000 mW
0.114 hp
0.085 kW
SP421 February 2018
345116328 MiB
8,192 KiB
8,388,608 B
0.00781 GiB
32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
2.15 GHz
2,150 MHz
2,150,000 kHz
3 GHz
3,000 MHz
3,000,000 kHz
DDR4-266640 °C
273.15 K
32 °F
491.67 °R
105 °C
378.15 K
221 °F
680.67 °R
80 W
80,000 mW
0.107 hp
0.08 kW
100 W
100,000 mW
0.134 hp
0.1 kW
SP421 February 2018$ 880.00
€ 792.00
£ 712.80
¥ 90,930.40
2028PE3451BMQGAAF
Count: 9

Photos[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Package Diagrams[edit]

SP4 diag.svg
SP4 package
  SP4r2 diag.svg
SP4r2 package

Pin Map[edit]

New text document.svg This section is empty; you can help add the missing info by editing this page.

Bibliography[edit]

See also[edit]

Facts about "Package SP4 - AMD"
designerAMD +
first launchedFebruary 21, 2018 +
instance ofpackage +
market segmentEmbedded +
microarchitectureZen +
nameSP4 +
tdp55 W (55,000 mW, 0.0738 hp, 0.055 kW) + and 100 W (100,000 mW, 0.134 hp, 0.1 kW) +