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=== Key changes from {{\\|Zen 2}} ===
 
=== Key changes from {{\\|Zen 2}} ===
 
* [[7_nm_lithography_process#N7.2B|7 nm+ process]] (from [[7 nm]]) , 20% more density and 10% power reduction compared to Zen 2.  EUV (Extreme Ultraviolet) lithography 7nm+.
 
* [[7_nm_lithography_process#N7.2B|7 nm+ process]] (from [[7 nm]]) , 20% more density and 10% power reduction compared to Zen 2.  EUV (Extreme Ultraviolet) lithography 7nm+.
* Decreasing the amount of CCXs per CCD from 2 to 1.
+
* Unify 2 x 4 core CCX into 1 x 8 core CCX per CCD.
 
* Decrease memory latency.
 
* Decrease memory latency.
  

Revision as of 08:07, 14 May 2020

Edit Values
Zen 3 µarch
General Info
Arch TypeCPU
DesignerAMD
ManufacturerTSMC
Introduction2020
Process7 nm+
Succession

Zen 3 is a planned microarchitecture being developed by AMD as a successor to Zen 2.

History

amd zen future roadmap.jpg

Zen 3 was formally disclosed in a roadmap by Lisa Su, AMD's CEO, during AMD's Tech Day in February of 2017. Zen 3 will be the 3rd iteration of the Zen microarchitecture. On Investor's Day in May 2017 Jim Anderson, AMD Senior Vice President, confirmed that Zen 3 is set to utilize 7nm+ process.

Codenames

amd zen2-3 roadmap.png
Symbol version future.svg Preliminary Data! Information presented in this article deal with future products, data, features, and specifications that have yet to be finalized, announced, or released. Information may be incomplete and can change by final release.
Core C/T Target
Milan  ?/? High-end server multiprocessors
Genesis Peak  ?/? Workstation & enthusiasts market processors
Vermeer  ?/? Mainstream to high-end desktops & enthusiasts market processors
Cezanne  ?/? Mainstream desktop & mobile processors with GPU

Process technology

Zen 3 will be fabricated on TSMC's 7nm+ process.

Architecture

Nothing is currently known about the architectural improvements that are being done for Zen 3.

Key changes from Zen 2

  • 7 nm+ process (from 7 nm) , 20% more density and 10% power reduction compared to Zen 2. EUV (Extreme Ultraviolet) lithography 7nm+.
  • Unify 2 x 4 core CCX into 1 x 8 core CCX per CCD.
  • Decrease memory latency.

This list is incomplete; you can help by expanding it.

References

  • AMD 'Tech Day', February 22, 2017
  • AMD 2017 Financial Analyst Day, May 16, 2017

See Also