From WikiChip
EPYC 7232P - AMD
< amd‎ | epyc
Revision as of 18:11, 4 January 2021 by QuietRub (talk | contribs) (Fixed clock multiplier, added missing data, added die count and memory bandwidth note.)

Edit Values
EPYC 7232P
General Info
ManufacturerTSMC, GlobalFoundries
Model Number7232P
Part Number100-000000081,
IntroductionAugust 7, 2019 (announced)
August 7, 2019 (launched)
Release Price$450
General Specs
Frequency3,100 MHz
Turbo Frequency3,200 MHz
Clock multiplier31
ISAx86-64 (x86)
MicroarchitectureZen 2
Core NameRome
Core Family23
Core Model49
Core SteppingB0
Process7 nm, 14 nm
MCPYes (2 dies)
Word Size64 bit
Max Memory4 TiB
Max SMP1-Way (Uniprocessor)
TDP120 W
PackageFCLGA-4094 (LGA)
Dimension58.5 mm × 75.4 mm
Pitch1.00 mm
SocketSocket SP3, LGA-4094

EPYC 7232P is a 64-bit octa-core x86 server microprocessor designed and introduced by AMD in mid-2019. This multi-chip processor, which is based on the Zen 2 microarchitecture, incorporates logic fabricated TSMC 7 nm process and I/O fabricated on GlobalFoundries 14 nm process. The 7232P has a TDP of 120 W with a base frequency of 3.1 GHz and a boost frequency of up to 3.2 GHz. This processor supports single-socket configurations only and up to 4 TiB of memory per socket.

This processor has 8 CPU cores and 32 MiB L3 cache. A single Core Complex Die (plus I/O die) can provide these resources, however there seems to be no evidence that AMD produces any Zen 2-based EPYC or Threadripper processors with an odd number of CCDs, and the advertised maximum memory bandwidth appears to exceed the capabilities of a single CCD. The EPYC 7252 SKU notably has the same specifications as this model except for supporting dual-socket systems and offering 64 MiB L3 cache which evidently requires two CCDs.


Main article: Zen 2 § Cache

[Edit/Modify Cache Info]

hierarchy icon.svg
Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory.

The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC.

Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies.

Note: All units are in kibibytes and mebibytes.
L1$512 KiB
0.5 MiB
524,288 B
4.882812e-4 GiB
L1I$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
8x32 KiB8-way set associative 
L1D$256 KiB
0.25 MiB
262,144 B
2.441406e-4 GiB
8x32 KiB8-way set associativewrite-back

L2$4 MiB
4,096 KiB
4,194,304 B
0.00391 GiB
  8x512 KiB8-way set associativewrite-back

L3$32 MiB
32,768 KiB
33,554,432 B
0.0313 GiB
  2x16 MiB  

Memory controller

This model supports up to 8 channels of up to DDR4-3200 memory[1][2] with a theoretical maximum bandwidth of 25.6 GB/s (≈ 23.84 GiB/s) per channel, but is apparently bandwidth limited by the IFOP links between the I/O die and its only one (two?) compute dies (effective bandwidth ≈ 55 GB/s per CCD at 1.46 GHz FCLK[3]). According to AMD this processor is "optimized for 4 channels with DDR4-2667 DIMMs" (≈ 21.3 GB/s per channel) and therefore has a "per-socket theoretical memory bandwidth 85.3 GB/s" (≈ 79.47 GiB/s).[2]

[Edit/Modify Memory Info]

ram icons.svg
Integrated Memory Controller
Max TypeDDR4-3200
Supports ECCYes
Max Mem4 TiB
Max Bandwidth190.7 GiB/s
331.818 GB/s
195,276.8 MiB/s
0.186 TiB/s
0.205 TB/s
Single 23.84 GiB/s
Double 47.68 GiB/s
Quad 95.37 GiB/s
Hexa 143.1 GiB/s
Octa 190.7 GiB/s


[Edit/Modify Expansions Info]

ide icon.svg
Expansion Options
PCIeRevision: 4.0
Max Lanes: 128
Configuration: x16, x8


[Edit/Modify Supported Features]

Supported x86 Extensions & Processor Features
MMXMMX Extension
EMMXExtended MMX Extension
SSEStreaming SIMD Extensions
SSE2Streaming SIMD Extensions 2
SSE3Streaming SIMD Extensions 3
SSSE3Supplemental SSE3
SSE4.1Streaming SIMD Extensions 4.1
SSE4.2Streaming SIMD Extensions 4.2
SSE4aStreaming SIMD Extensions 4a
AVXAdvanced Vector Extensions
AVX2Advanced Vector Extensions 2
ABMAdvanced Bit Manipulation
BMI1Bit Manipulation Instruction Set 1
BMI2Bit Manipulation Instruction Set 2
FMA33-Operand Fused-Multiply-Add
AESAES Encryption Instructions
RdRandHardware RNG
SHASHA Extensions
ADXMulti-Precision Add-Carry
CLMULCarry-less Multiplication Extension
F16C16-bit Floating Point Conversion
x86-1616-bit x86
x86-3232-bit x86
x86-6464-bit x86
RealReal Mode
ProtectedProtected Mode
SMMSystem Management Mode
FPUIntegrated x87 FPU
SMTSimultaneous Multithreading
AMD-ViAMD-Vi (I/O MMU virtualization)
AMD-VAMD Virtualization
SMESecure Memory Encryption
TSMETransparent SME
SEVSecure Encrypted Virtualization
SenseMISenseMI Technology
Boost 2Precision Boost 2


  1. "AMD EPYC™ 7232p". Retrieved October 2020.
  2. 2.0 2.1 "AMD EPYC™ 7002 Series Processors: A New Standard for the Modern Datacenter", AMD Publ. #LE-70002, Rev. 02, April 2020
  3. Naffziger, Samuel; Lepak, Kevin; Paraschou, Milam; Subramony, Mahesh (2020). 2.2 AMD Chiplet Architecture for High-Performance Server and Desktop Products. 2020 IEEE International Solid-State Circuits Conference. pp. 44-45. doi:10.1109/ISSCC19947.2020.9063103
Facts about "EPYC 7232P - AMD"
Has subobject
"Has subobject" is a predefined property representing a container construct and is provided by Semantic MediaWiki.
EPYC 7232P - AMD#pcie +
base frequency3,100 MHz (3.1 GHz, 3,100,000 kHz) +
clock multiplier31 +
core count8 +
core family23 +
core model49 +
core nameRome +
core steppingB0 +
designerAMD +
die count2 +
familyEPYC +
first announcedAugust 7, 2019 +
first launchedAugust 7, 2019 +
full page nameamd/epyc/7232p +
has advanced vector extensionstrue +
has advanced vector extensions 2true +
has amd amd-v technologytrue +
has amd amd-vi technologytrue +
has amd precision boost 2true +
has amd secure encrypted virtualization technologytrue +
has amd secure memory encryption technologytrue +
has amd sensemi technologytrue +
has amd transparent secure memory encryption technologytrue +
has ecc memory supporttrue +
has featureAdvanced Vector Extensions +, Advanced Vector Extensions 2 +, Advanced Encryption Standard Instruction Set Extension +, SenseMI Technology + and Precision Boost 2 +
has locked clock multipliertrue +
has simultaneous multithreadingtrue +
has x86 advanced encryption standard instruction set extensiontrue +
instance ofmicroprocessor +
is multi-chip packagetrue +
isax86-64 +
isa familyx86 +
l1$ size0.5 MiB (512 KiB, 524,288 B, 4.882812e-4 GiB) +
l1d$ description8-way set associative +
l1d$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
l1i$ description8-way set associative +
l1i$ size0.25 MiB (256 KiB, 262,144 B, 2.441406e-4 GiB) +
l2$ description8-way set associative +
l2$ size4 MiB (4,096 KiB, 4,194,304 B, 0.00391 GiB) +
l3$ size32 MiB (32,768 KiB, 33,554,432 B, 0.0313 GiB) +
ldateAugust 7, 2019 +
manufacturerTSMC + and GlobalFoundries +
market segmentServer +
max cpu count1 +
max memory4,194,304 MiB (4,294,967,296 KiB, 4,398,046,511,104 B, 4,096 GiB, 4 TiB) +
max memory bandwidth190.7 GiB/s (331.818 GB/s, 195,276.8 MiB/s, 0.186 TiB/s, 0.205 TB/s) +
max memory channels8 +
microarchitectureZen 2 +
model number7232P +
nameEPYC 7232P +
packageFCLGA-4094 +
part number100-000000081 + and 100-000000081WOF +
process7 nm (0.007 μm, 7.0e-6 mm) + and 14 nm (0.014 μm, 1.4e-5 mm) +
release price$ 450.00 (€ 405.00, £ 364.50, ¥ 46,498.50) +
series7002 +
smp max ways1 +
socketSocket SP3 + and LGA-4094 +
supported memory typeDDR4-3200 +
tdp120 W (120,000 mW, 0.161 hp, 0.12 kW) +
technologyCMOS +
thread count16 +
turbo frequency3,200 MHz (3.2 GHz, 3,200,000 kHz) +
word size64 bit (8 octets, 16 nibbles) +