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(Architecture)
(Architecture)
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[[File:ambric neighbor channels.png|thumb|right|350px|'''Neighbor Channels''']]
 
[[File:ambric neighbor channels.png|thumb|right|350px|'''Neighbor Channels''']]
 
Ambric's architecture makes heavy use of channels - synchronized interconnects that carry both data and instructions in a [[FIFO]]. Channels are a strong point of this architecture as all data goes through channels including [[memory]] and [[registers]]. Channel interconnects can be loosely divided into three categories:  
 
Ambric's architecture makes heavy use of channels - synchronized interconnects that carry both data and instructions in a [[FIFO]]. Channels are a strong point of this architecture as all data goes through channels including [[memory]] and [[registers]]. Channel interconnects can be loosely divided into three categories:  
 +
  
 
* '''Intra-Bric Channels''': internal channels that span no loner than a single bric. All basic communication utilizes these channels. They are dynamically configured by the instructions themselves. Typical ALU [[register]]/[[memory]] utilizes these channels.  
 
* '''Intra-Bric Channels''': internal channels that span no loner than a single bric. All basic communication utilizes these channels. They are dynamically configured by the instructions themselves. Typical ALU [[register]]/[[memory]] utilizes these channels.  
 +
  
 
* '''Neighbor Channels''': channels spanning between two CU units. These channels only go to an adjacent control unit (i.e. directly North, South, East, or West). Only one channel is aviable in each direction. Channels are {{arch|32}} wide operating at up to 9.6 GT/s.
 
* '''Neighbor Channels''': channels spanning between two CU units. These channels only go to an adjacent control unit (i.e. directly North, South, East, or West). Only one channel is aviable in each direction. Channels are {{arch|32}} wide operating at up to 9.6 GT/s.
 +
  
 
* '''Inter-Bric Channels''': also known as distanced bric channels, are communication channels that operate globally between any two brics. Switches are located at each of the control units (CUs). Routes are configured  
 
* '''Inter-Bric Channels''': also known as distanced bric channels, are communication channels that operate globally between any two brics. Switches are located at each of the control units (CUs). Routes are configured  
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* 2x '''Compute Units''' (CU)
 
* 2x '''Compute Units''' (CU)
 
::Each Compute Unit contains 2x '''SRD''' {{arch|32}} CPUs and 2x '''SR''' {{arch|32}} CPUs. Channel interconnects are also handled in this area.
 
::Each Compute Unit contains 2x '''SRD''' {{arch|32}} CPUs and 2x '''SR''' {{arch|32}} CPUs. Channel interconnects are also handled in this area.
 +
  
 
* 2x '''RAM Units''' (RU)
 
* 2x '''RAM Units''' (RU)
::Each RAM Unit contains 4 2 kB RAM banks, each indepdently accessed via a dynamically programmed channel operating in FIFO and random access modes via the RU engines.
+
::Each RAM Unit contains 4 2 kB RAM banks, each independently accessed via a dynamically programmed channel operating in FIFO and random access modes via the RU engines.
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{{clear}}
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==== SR Processor ====
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[[File:ambric sr core instruction.png|right]]
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The '''SR''' ('''Streaming [[RISC]]''') Processor is a {{arch|32}} processor for fast simple operations. This processor can handle complex [[addressing]], [[serialization]] and [[deserialization]]. Each processor has 2 input channels and 1 output channel - all of which are controlled by the instructions themselves. Additionally, the processor includes:
 +
 
 +
* 1x ALU - 1x {{arch|32}} OR 2x {{arch|16}} operations
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* 8x [[general-purpose registers|General Purpose]] [[register|Registers]]
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* {{arch|16}} instruction word size
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* 3-stage channel datapath
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* 64 word local code/data RAM
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 +
[[File:ambric sr core.png]]
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{{clear}}
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==== SRD Processor ====
 +
[[File:ambric srd core instruction.png|right]]
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The '''SRD''' ('''Streaming [[RISC]] with [[DSP]] extensions''') Processor is a {{arch|32}} processor for more complex operations that may benefit from [[instruction-level parallelism]] and iterative algorithms. Each processor has 2 input channels and 1 output channel - all of which are controlled by the instructions themselves. Additionally, the processor includes:
 +
 
 +
* 3x ALU
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** 2x ALU in serial
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*** 1x {{arch|32}} OR 2x {{arch|16}} OR 4x {{arch|8}} operations
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** 1x ALU in parallel
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*** 1x {{arch|32}} * {{arch|8}} OR 2x {{arch|16}} * {{arch|8}}, 1x {{arch|64}} [[accumulator]], etc..
  
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[[File:ambric srd core.png]]
 
{{clear}}
 
{{clear}}
  

Revision as of 23:42, 24 June 2016

Ambric Am2000
ambric 2045.gif
Am2045
Developer Ambric
Manufacturer TSMC
Type Microprocessors
Introduction October 10, 2006 (announced)
December, 2006 (launch)
Architecture Many-core 32-bit microprocessor
Word size 32 bit
4 octets
8 nibbles
Process 130 nm
0.13 μm
1.3e-4 mm
Technology CMOS
Clock 1 MHz-333 Mhz
Package FCBGA-868, FCBGA-896

Am2000 was a family of 32-bit MPPAs designed by Ambric. The series was introduced at the 2006 Fall Microprocessor Forum. The two flagship models the Am2045 (A) and later Am2045B had over 300 cores with maximum theoretical performance of over one trillion operations per second. Due to the economic downturn of 2008 Ambric failed to secure additional funding and was forced to sell its assets to Nethra Imaging which continued to manufacture the chips until 2013. Prior to the acquisition Ambric also announced a 600 cores, 600 MHz model. It's unknown if the model ever made it to market. Designs, software, and related patents are now held by Imagination Technologies.

Ambric, unlike many of its competitors, managed to develop a sound programming model that proved itself to be simple enough and intuitive enough to allow easy programming. Am2000 found their way to various military applications, medical instruments, and high-end multimedia hardware.

Overview

Introduced in the fall of 2006, the Am2000 is a series of many-core processors implemented as a massively parallel processor array designed to replace high-end embedded processors, DSPs, and FPGAs in applications where fast general-purpose integer arithmetic and digital-signal processing is required. Such tasks usually land themselves fairly well in highly parallel environments.

Ambric's AM2000 series is an example of one of the few massively parallel processors that succeeded in independently developing a solid programming model and tools that worked extremely well with the underlying processor that relatively easy to code. A complete set of development tools were also offered with the product including extensions to Eclipse IDE. Code for the AM2000 used a language called aJava which was a strict subset of Java that compiled directly into machine code.

Members

,,,,,,,
Am2000 Models
ModelLaunchedProcessFreqCore Count
Am2012January 2007130 nm
0.13 μm
1.3e-4 mm
333 MHz
0.333 GHz
333,000 kHz
96
Am201615 November 2007130 nm
0.13 μm
1.3e-4 mm
350 MHz
0.35 GHz
350,000 kHz
120
Am2024January 2007130 nm
0.13 μm
1.3e-4 mm
333 MHz
0.333 GHz
333,000 kHz
192
Am202915 November 2007130 nm
0.13 μm
1.3e-4 mm
350 MHz
0.35 GHz
350,000 kHz
216
Am2035January 2007130 nm
0.13 μm
1.3e-4 mm
333 MHz
0.333 GHz
333,000 kHz
280
Am2045January 2007130 nm
0.13 μm
1.3e-4 mm
333 MHz
0.333 GHz
333,000 kHz
344
Am2045B15 November 2007130 nm
0.13 μm
1.3e-4 mm
350 MHz
0.35 GHz
350,000 kHz
344
Am207090 nm
0.09 μm
9.0e-5 mm
600 MHz
0.6 GHz
600,000 kHz
560
Count: 8

Architecture

Ambric's Am2000 models are all made of small homogeneous units called Brics. The exact number of brics depends on the model.

Communication

Neighbor Channels

Ambric's architecture makes heavy use of channels - synchronized interconnects that carry both data and instructions in a FIFO. Channels are a strong point of this architecture as all data goes through channels including memory and registers. Channel interconnects can be loosely divided into three categories:


  • Intra-Bric Channels: internal channels that span no loner than a single bric. All basic communication utilizes these channels. They are dynamically configured by the instructions themselves. Typical ALU register/memory utilizes these channels.


  • Neighbor Channels: channels spanning between two CU units. These channels only go to an adjacent control unit (i.e. directly North, South, East, or West). Only one channel is aviable in each direction. Channels are 32-bit wide operating at up to 9.6 GT/s.


  • Inter-Bric Channels: also known as distanced bric channels, are communication channels that operate globally between any two brics. Switches are located at each of the control units (CUs). Routes are configured

Brics

ambric bric.png

Bric is the fundamental building block. Each block contains:

  • 2x Compute Units (CU)
Each Compute Unit contains 2x SRD 32-bit CPUs and 2x SR 32-bit CPUs. Channel interconnects are also handled in this area.


  • 2x RAM Units (RU)
Each RAM Unit contains 4 2 kB RAM banks, each independently accessed via a dynamically programmed channel operating in FIFO and random access modes via the RU engines.

SR Processor

ambric sr core instruction.png

The SR (Streaming RISC) Processor is a 32-bit processor for fast simple operations. This processor can handle complex addressing, serialization and deserialization. Each processor has 2 input channels and 1 output channel - all of which are controlled by the instructions themselves. Additionally, the processor includes:

ambric sr core.png

SRD Processor

ambric srd core instruction.png

The SRD (Streaming RISC with DSP extensions) Processor is a 32-bit processor for more complex operations that may benefit from instruction-level parallelism and iterative algorithms. Each processor has 2 input channels and 1 output channel - all of which are controlled by the instructions themselves. Additionally, the processor includes:

ambric srd core.png

Programming

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Applications

The Am2000 has been used for high-definition video processing, medical imaging devices, high performance network processing, image recognition, and various military applications such as drones.

See also

Facts about "Am2000 - Ambric"
designerAmbric +
first announcedOctober 10, 2006 +
first launchedDecember 2006 +
full page nameambric/am2000 +
instance ofmicroprocessor family +
main designerAmbric +
manufacturerTSMC +
nameAmbric Am2000 +
packageFCBGA-868 + and FCBGA-896 +
process130 nm (0.13 μm, 1.3e-4 mm) +
technologyCMOS +
word size32 bit (4 octets, 8 nibbles) +