Semiconductor & Computer Engineering
-
WikiChip
WikiChip
-
Architectures
Popular x86
-
Intel
- Client
- Server
- Big Cores
- Small Cores
-
AMD
Popular ARM
-
ARM
- Server
- Big
- Little
-
Cavium
-
Samsung
-
-
Chips
Popular Families
-
Ampere
-
Apple
-
Cavium
-
HiSilicon
-
MediaTek
-
NXP
-
Qualcomm
-
Renesas
-
Samsung
-
From WikiChip
Revision history of "alchemy/microarchitectures/au1"
Diff selection: Mark the radio boxes of the revisions to compare and hit enter or the button at the bottom.
Legend: (cur) = difference with latest revision, (prev) = difference with preceding revision, m = minor edit.
Retrieved from "https://en.wikichip.org/wiki/alchemy/microarchitectures/au1"
Facts about "Au1 - Microarchitectures - Alchemy"
| codename | Au1 + |
| core count | 1 + |
| designer | Alchemy + |
| first launched | June 13, 2000 + |
| full page name | alchemy/microarchitectures/au1 + |
| instance of | microarchitecture + |
| instruction set architecture | MIPS32 + |
| manufacturer | TSMC + |
| microarchitecture type | CPU + |
| name | Au1 + |
| pipeline stages | 5 + |
| process | 180 nm (0.18 μm, 1.8e-4 mm) + and 130 nm (0.13 μm, 1.3e-4 mm) + |
