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2024-03-29T15:46:53Z
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QuietRub: Created page with "{{title|Alchemy Au1250-600MGD}} {{chip |name=Alchemy Au1250-600MGD |no image=Yes |designer=RMI |model number=Au1250-600MGD |part number=Au1250-600MGD |market=Embedded |first a..."
2022-03-19T06:00:52Z
<p>Created page with "{{title|Alchemy Au1250-600MGD}} {{chip |name=Alchemy Au1250-600MGD |no image=Yes |designer=RMI |model number=Au1250-600MGD |part number=Au1250-600MGD |market=Embedded |first a..."</p>
<p><b>New page</b></p><div>{{title|Alchemy Au1250-600MGD}}<br />
{{chip<br />
|name=Alchemy Au1250-600MGD<br />
|no image=Yes<br />
|designer=RMI<br />
|model number=Au1250-600MGD<br />
|part number=Au1250-600MGD<br />
|market=Embedded<br />
|first announced=January 9, 2007<br />
|first launched=June 5, 2007<br />
|last order=<br />
|last shipment=<br />
|release price (tray)=<br />
|family=Alchemy<br />
|frequency=600 MHz<br />
|isa=MIPS32<br />
|microarch=Au1<br />
|platform=<br />
|chipset=<br />
|manufacturer=<br />
|process=<br />
|transistors=<br />
|technology=CMOS<br />
|die area=<br />
|word size=32 bit<br />
|core count=1<br />
|max cpus=1<br />
|max memory=512 MiB<br />
|v core=1.2 V<br />
|v core tolerance=10%<br />
|v io=3.3 V<br />
|tdp=1400 mW<br />
|tdp typical=580 mW<br />
|tcase min=0 °C<br />
|tcase max=70 °C<br />
|tstorage min=-40 °C<br />
|tstorage max=125 °C<br />
}}<br />
'''Au1250-600MGD''' was a {{arch|32}} ultra low power embedded microprocessor with an {{alchemy|Au1|l=arch}} CPU core implementing the [[MIPS32]] ISA. Designed by [[RMI]] based on {{alchemy|alchemy|earlier}} [[AMD]] and [[Alchemy Semiconductor]] processors this {{abbr|SoC}} operates at a base frequency of up to 600 MHz with a typical {{abbr|TDP}} of 580 mW and maximum TDP of 1400 mW. <br />
<br />
== Cache ==<br />
{{main|alchemy/microarchitectures/au1#Memory_Hierarchy|l1=Au1 § Cache}}<br />
{{cache size<br />
|l1 cache=32 KiB<br />
|l1i cache=16 KiB<br />
|l1i break=1 × 16 KiB<br />
|l1i desc=4-way set associative<br />
|l1d cache=16 KiB<br />
|l1d break=1 × 16 KiB<br />
|l1d desc=4-way set associative<br />
|l1d policy=write-back<br />
}}<br />
<br />
== Memory controller ==<br />
Au1250 processors integrate two independent memory controllers, a DRAM controller which supports 2.5&nbsp;V DDR and 1.8&nbsp;V DDR2 SDRAM devices, and a static bus controller which supports SRAM, ROM, NAND Flash, NOR Flash, {{abbr|PCMCIA}}/CompactFlash devices, IDE PIO mode, and other I/O peripherals. The CPU core, the memory controllers, and other integrated peripherals are linked by an internal 32-bit System Bus (SBUS). The SDRAM clock is configurable 1/1 or 1/2 of the SBUS frequency, which is configurable 1/2, 1/3, or 1/4 of the core frequency. The integrated LCD and MAE peripherals can access the SDRAM controller through a 64-bit side bus running at the SBUS frequency. <br />
<br />
{{memory controller<br />
|type=DDR-400<br />
|type 2=DDR2-533<br />
|ecc=No<br />
|controllers=1<br />
|channels=1<br />
|max mem=512 MiB<br />
|width=16 bit<br />
|width 2=32 bit<br />
|max bandwidth=1.600 GB/s<br />
}}<br />
<br />
== Expansions ==<br />
* USB 2.0 ({{abbr|EHCI}}) and 1.1 ({{abbr|OHCI}}) host controller, USB 2.0 device controller with OTG support<br />
** One USB host port and one host/device port, each low/fast/high speed capable<br />
* Two [[wikipedia:SD card|Secure Digital]]/{{abbr|SDHC}}/{{abbr|SDIO}}/{{abbr|MMC}} 1.1 controllers<br />
* Two Programmable Serial Controllers supporting the {{abbr|AC97}}, {{abbr|I2S}}, {{abbr|SPI}}, and {{abbr|SMBus}} protocols<br />
* Two {{abbr|UART}}s<br />
* Up to 48 {{abbr|GPIO}}s<br />
<br />
== Graphics ==<br />
This processor integrates an LCD controller for panels with a resolution up to 2048 × 2048 pixels.<br />
* TFT: 1/2/4/8-bit mono, 12/16/18/24-bit color<br />
* STN: 4/8-bit mono single-scan, 8-bit color single-scan, 16-bit color dual-scan<br />
* Frame buffer formats:<br />
** 1/2/4/8-bpp pass through/grayscale/palettized<br />
** 16-bpp 6:5:5, 5:6:5, 5:5:6, 5:5:5:1, 4:4:4:0<br />
** 24-bpp 8:8:8:0<br />
** 32-bpp 8:8:8:8 RGBA<br />
* Four overlay windows with double buffering<br />
* Gamma correction, alpha blending, and chroma keying<br />
* 32 × 32 × 2 bpp hardware cursor<br />
<br />
== Features ==<br />
* Camera Interface Module (CIM)<br />
** [[wikipedia:ITU-R BT.656|ITU-R BT.656]] compatible 8/9/10-bit bus running at up to 33 MHz<br />
** Support for UYVY and Bayer RGB to planar format conversion<br />
* Media Acceleration Engine (MAE) to accelerate video decoding in hardware<br />
** Formats MPEG-1/2/4, DivX-3/4/5, H.263, WMV9, VC-1<br />
** Accelerates inverse quantization, inverse DCT, motion compensation, WMV9 filters<br />
** Hardware colorspace conversion and scaling with 4-tap filter, also for CIM<br />
** Video decode resolution up to D1 720 × 480 NTSC / 720 × 576 PAL<br />
* 16-channel descriptor-based DMA controller<br />
** Memory to memory, memory to peripheral, peripheral to memory, peripheral to peripheral<br />
** 36-bit source and destination addresses with no alignment requirement<br />
** Scatter/gather and stride transfers<br />
** Compare and branch descriptors<br />
* AES-128 encryption/decryption in hardware with ECB, CBC, CFB, and OFB block cipher modes<br />
* {{abbr|RTC}} and {{abbr|TOY|Time Of Year}} timer<br />
* Two interrupt controllers<br />
* Power management unit<br />
* MIPS EJTAG interface<br />
* Idle, Sleep, Hibernate Mode<br />
<br />
== Package ==<br />
* 372-pin low profile, fine pitch plastic ball grid array (LF-PBGA) package<br />
* 23 × 23 grid, 0.8&nbsp;mm pitch<br />
* 19&nbsp;mm × 19&nbsp;mm × 1.4&nbsp;mm<br />
<br />
== Bibliography ==<br />
* {{cite techdoc|title=RMI Alchemy™ Au1210™ Navigation Processor and Au1250™ Media Processor Data Book|file=RMI-Au1210-Au1250-DB.pdf|publ=RMI Corp.|rev=A|date=2007-04}}</div>
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