From WikiChip
adder
Revision as of 08:08, 15 December 2015 by 122.178.254.3 (talk) (Brent Kung Adder)

An adder (sometimes called a summer) is a digital circuit that adds two N-bit numbers and generates an N-bit number. In addition to generating a sum, adders often also generate an overflow flag and a carry flag. Adders are used in many parts of the microprocessor such as the ALU, PC, counters, calculating effective addresses and table indices, multipliers, filters, and in various other components.

Basic design

Equation StartLayout 1st Row 1st Column upper A plus upper B 2nd Column equals upper Q 2nd Row 1st Column 0 Subscript 2 Baseline plus 0 Subscript 2 2nd Column equals 00 Subscript 2 Baseline 3rd Row 1st Column 0 Subscript 2 Baseline plus 1 Subscript 2 2nd Column equals 01 Subscript 2 Baseline 4th Row 1st Column 1 Subscript 2 Baseline plus 0 Subscript 2 2nd Column equals 01 Subscript 2 Baseline 5th Row 1st Column 1 Subscript 2 Baseline plus 1 Subscript 2 2nd Column equals 10 Subscript 2 EndLayout A 1-bit adder adds two single-bit values together. There are four such possible operations. All but the 1+1 operation result in a single-digit sum. The 1+1 operation produces a sum with two digits. The higher significant bit of that value is known as a carry. The digital component that performs the addition of two bits is called a half adder. When two multi-bit numbers are added together, the carry out from the lower bit must be accounted for in the higher addition of the higher bits. When a half adder accounts for a carry in, it becomes a full adder.

Half Adders (HA)

Main article: Half adder
Half Adder
Input Cout S Q10
0 0 0 0 0
0 1 0 1 1
1 0 0 1 1
1 1 1 0 2
1-bit addition.svg

A half adder is a simple device that adds two single bit inputs. The result of a half adder (in base 10) is either 0, 1, or 2. Two bits are required to represent that output; they are called the sum S and carry-out Cout. The carry-out of one half adder is typically used as the carry-in of the next half adder. For that reason it is said to have double the weight of the other bit.

The sum is 1 only when one of the operands is 1, otherwise it's 0. This can be realized by simply XORing them together. The carry out bit is one only when both addends are one; ANDing the two bits will generate the desired output.

Equation StartLayout 1st Row 1st Column upper S equals 2nd Column upper A circled-plus upper B 2nd Row 1st Column upper C Subscript o u t Baseline equals 2nd Column upper A dot upper B EndLayout

Full Adder (FA)

Main article: full adder
Full adder black box.svg

A major drawback of a half adder is that it lacks the ability to add two bits and account for a carry-in that might have been brought from the previous digit. As previously stated, the carry-out of one half adder is the carry-in of the next half adder. A full adder is a simple device that can receive a carry-in bit input in addition to adding two single bit inputs. A full adder has three inputs A, B, and Cin and two outputs S and Cout. Full adders are typically combined together in a cascading way (Cin to out), creating N-bit adders (16, 32, 64, etc..).

The sum output can be expressed as:

Equation StartLayout 1st Row 1st Column upper S equals 2nd Column upper A circled-plus upper B circled-plus upper C 2nd Row 1st Column upper C Subscript o u t Baseline equals 2nd Column Maj left-parenthesis upper A comma upper B comma upper C right-parenthesis EndLayout

BCD Adders

Main article: BCD Adder


Most adders typically use the binary numeral system, however they can use any other numerical representation such as binary-coded decimal. Binary adders are typically simpler to design when compared to a BCD adder where roughly 20 percent more circuitry is required.

Advanced Designs

Due to the adder's central role in so many digital circuits, it has been the subject of many researches. Various different designs have been developed over the years to meet a broad range of requirements (e.g. complexity, cost, space, and time trade-offs).

PGK Cell

New text document.svg This section is empty; you can help add the missing info by editing this page.

Many complex adder designs relay on the ability to calculate carry bits quickly.

Two-operand adders

Ripple-carry adder (RCA)

Main article: Ripple-carry adder
New text document.svg This section is empty; you can help add the missing info by editing this page.

Carry-lookahead adder (CLA)

Main article: Carry-lookahead adder
New text document.svg This section is empty; you can help add the missing info by editing this page.
Lookahead carry unit (LCU)
Main article: Lookahead carry unit
New text document.svg This section is empty; you can help add the missing info by editing this page.
Ripple-block carry-lookahead adder (RCLA)
Main article: Ripple-block carry-lookahead adder
New text document.svg This section is empty; you can help add the missing info by editing this page.
Block carry-lookahead adder (BCLA)
Main article: Block carry-lookahead adder
New text document.svg This section is empty; you can help add the missing info by editing this page.

Ling adder

Main article: Ling adder
New text document.svg This section is empty; you can help add the missing info by editing this page.

Manchester carry-chain adder

Main article: Manchester carry-chain adder
New text document.svg This section is empty; you can help add the missing info by editing this page.

Carry-select adder

Main article: Carry-select adder
New text document.svg This section is empty; you can help add the missing info by editing this page.

Carry-skip adder

Main article: Carry-skip adder
New text document.svg This section is empty; you can help add the missing info by editing this page.

Conditional-Sum Adder

Main article: Conditional-sum adder
New text document.svg This section is empty; you can help add the missing info by editing this page.

Parallel-prefix adders

Main article: Parallel-prefix adder

Parallel prefix adders are a class of highly-efficient binary adders. Several parallel-prefix adder topologies have been developed that exhibit various space and time characteristics.

Beaumont-Smith adder (BSA)
Main article: Beaumont-Smith adder
New text document.svg This section is empty; you can help add the missing info by editing this page.
Ladner-Fischer adder
Main article: Ladner-Fischer adder
New text document.svg This section is empty; you can help add the missing info by editing this page.
Kogge-Stone adder
Main article: Kogge-Stone adder
New text document.svg This section is empty; you can help add the missing info by editing this page.
Brent-Kung adder
Main article: Brent-Kung adder

{{Brent-Kung adder is a very well-known logarithmic adder architecture that gives an optimal number of stages from input to all outputs but with asymmetric loading on all intermediate stages. It is one of the parallel prefix adders. Parallel prefix adders are unique class of adders that are based on the use of generate and propagate signals. The cost and wiring complexity is less in brent kung adders. But the gate level depth of Brent-Kung adders is 0 (log2(n)), so the speed is lower.}}

Han-Carlson adder
Main article: Han-Carlson adder
New text document.svg This section is empty; you can help add the missing info by editing this page.

Multi-operand adders

(Partial product accumulator)

Carry-save adder array

Main article: Carry-save adder array
New text document.svg This section is empty; you can help add the missing info by editing this page.

Wallace tree adder

Main article: Wallace tree adder
New text document.svg This section is empty; you can help add the missing info by editing this page.

Balanced delay tree adder

Main article: Balanced delay tree adder
New text document.svg This section is empty; you can help add the missing info by editing this page.

Overturned-stairs tree adder

Main article: Overturned-stairs tree adder
New text document.svg This section is empty; you can help add the missing info by editing this page.

Compressors trees

New text document.svg This section is empty; you can help add the missing info by editing this page.
3:2 compressor tree
Main article: 3:2 compressor tree
New text document.svg This section is empty; you can help add the missing info by editing this page.
4:2 compressor tree
Main article: 4:2 compressor tree
New text document.svg This section is empty; you can help add the missing info by editing this page.
Dadda tree
Main article: Dadda tree
New text document.svg This section is empty; you can help add the missing info by editing this page.