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== All ARM2 Chips ==
 
== All ARM2 Chips ==
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<table class="comptable sortable tc11 tc12 tc13">
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<tr class="comptable-header"><th>&nbsp;</th><th colspan="12">List of ARM2-based Processors</th></tr>
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== References ==
 
== References ==
 
* Furber, S. B., and A. R. Wilson. "The Acorn RISC Machine ߞ an architectural view." Electronics and Power 33.6 (1987): 402-405.
 
* Furber, S. B., and A. R. Wilson. "The Acorn RISC Machine ߞ an architectural view." Electronics and Power 33.6 (1987): 402-405.

Revision as of 18:02, 30 June 2017

Edit Values
ARM2 µarch
General Info
Arch TypeCPU
DesignerAcorn Computers
ManufacturerVLSI Technology, Sanyo
Introduction1986
Process2 µm
Core Configs1
Pipeline
TypeScalar, Pipelined
Stages3
Decode1-way
Instructions
ISAARMv2
Cache
L1I Cache0 KiB/Core
L1D Cache0 KiB/Core
Succession

ARM2 is the second ARM implementation designed by Acorn Computers as a successor to the ARM1. Introduced in 1986, the ARM2 brings a number of major improvements over its predecessor.

Overview

See also: ARM's History

Introduced in 1986, the ARM2 is a reimplementation of the ARM1 on a smaller process along with the addition of a number of additional enhancements. The ARM2 was capable of exceeding 10 MIPS when not bottlenecked by memory with an average of around 6 MIPS. Unlike the ARM1 which was predominantly a research project, the ARM2 became the first commercially successful ARM microprocessor.

The ARM2 was designed to work as an embedded controller or a coprocessor or as a stand-alone microprocessor system. The Acorn Archimedes family of personal computers was built using the ARM2 along with a number of fully custom support chips that were also designed by Acorn Computer.

Process Technology

See also: 2 µm process

ARM2 chips were manufactured by VLSI Technology and Sanyo on a 2 µm double-level metal CMOS process.

Architecture

Key changes from ARM1

  • 2 µm process (from 3 µm)
  • > 2x MIPS when not bottlenecked by memory
  • 27-entry register file (from 25)
    • 2 new program status registers
    • Aid Fast Interrupts
  • New support for coprocessors
  • New support for hardware multiply and accumulate

New instructions

ARM2 introduces a number of new instructions to deal with the new features:

Coprocessor:

  • CDP - Coprocessor data process
  • LDC - Load to coprocessor
  • STC - Store from coprocessor
  • MCR - Move to coprocessor
  • MRC - Move from coprocessor

Arithmetics:

  • MUL - Multiplication
  • MLA - Multiplication and accumulate

Block Diagram

Core

arm2 block diagram.svg

Core

Pipeline

New text document.svg This section is empty; you can help add the missing info by editing this page.

Die

All ARM2 Chips

 List of ARM2-based Processors
ModelProcessLaunchedFrequencyPower DissipationMax Memory
Count: 0

References

  • Furber, S. B., and A. R. Wilson. "The Acorn RISC Machine ߞ an architectural view." Electronics and Power 33.6 (1987): 402-405.
codenameARM2 +
core count1 +
designerAcorn Computers +
first launched1986 +
full page nameacorn/microarchitectures/arm2 +
instance ofmicroarchitecture +
instruction set architectureARMv2 +
manufacturerVLSI Technology + and Sanyo +
microarchitecture typeCPU +
nameARM2 +
pipeline stages3 +
process2,000 nm (2 μm, 0.002 mm) +