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Difference between revisions of "acorn/microarchitectures/arm2"
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(Key changes from {{\\|ARM1}})
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== Overview ==
 
== Overview ==
 
{{see also|arm/history|l1=ARM's History}}
 
{{see also|arm/history|l1=ARM's History}}
Introduced in 1986, the ARM2 is a reimplementation of the {{\\|ARM1}} on a smaller process along with the addition of a number of additional enhancements. The ARM2 was capable of exceeding 10 MIPS when not bottlenecked by memory.
+
Introduced in 1986, the ARM2 is a reimplementation of the {{\\|ARM1}} on a smaller process along with the addition of a number of additional enhancements. The ARM2 was capable of exceeding 10 MIPS when not bottlenecked by memory with an average of around 6 MIPS. Unlike the ARM1 which was predominantly a research project, the ARM2 became the first commercially successful ARM microprocessor.
  
 
== Process Technology ==
 
== Process Technology ==
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* 27-entry register file (from 25)
 
* 27-entry register file (from 25)
 
** 2 new program status registers
 
** 2 new program status registers
 +
** Aid Fast Interrupts
 +
* New support for coprocessors
 +
* New support for hardware multiply and accumulate
 +
 +
==== New instructions ====
 +
ARM2 introduces a number of new instructions to deal with the new features:
 +
 +
'''Coprocessor:'''
 +
 +
* <code>CDP</code> - Coprocessor data process
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* <code>LDC</code> - Load to coprocessor
 +
* <code>STC</code> - Store to coprocessor
 +
* <code>MCR</code> - Move to coprocessor
 +
* <code>MRC</code> - Move from coprocessor
 +
 +
'''Arithmetics:'''
 +
* <code>MUL</code> - Multiplication
 +
* <code>MLA</code> - Multiplication and accumulate
  
 
=== Block Diagram ===
 
=== Block Diagram ===

Revision as of 01:59, 28 June 2017

Edit Values
ARM2 µarch
General Info
Arch TypeCPU
DesignerARM Holdings
ManufacturerVLSI Technology, Sanyo
Introduction1986
Process2 µm
Core Configs1
Pipeline
TypeScalar, Pipelined
Stages3
Decode1-way
Instructions
ISAARMv2
Cache
L1I Cache0 KiB/Core
L1D Cache0 KiB/Core
Succession

ARM2 is the second ARM implementation designed by ARM Holdings (then Acorn Computers) as a successor to the ARM1. Introduced in 1986, the ARM2 brings a number of major improvements over its predecessor.

Overview

See also: ARM's History

Introduced in 1986, the ARM2 is a reimplementation of the ARM1 on a smaller process along with the addition of a number of additional enhancements. The ARM2 was capable of exceeding 10 MIPS when not bottlenecked by memory with an average of around 6 MIPS. Unlike the ARM1 which was predominantly a research project, the ARM2 became the first commercially successful ARM microprocessor.

Process Technology

See also: 2 µm process

ARM2 chips were manufactured by VLSI Technology and Sanyo on a 2 µm double-level metal CMOS process.

Architecture

Key changes from ARM1

  • 2 µm process (from 3 µm)
  • > 2x MIPS when not bottlenecked by memory
  • 27-entry register file (from 25)
    • 2 new program status registers
    • Aid Fast Interrupts
  • New support for coprocessors
  • New support for hardware multiply and accumulate

New instructions

ARM2 introduces a number of new instructions to deal with the new features:

Coprocessor:

  • CDP - Coprocessor data process
  • LDC - Load to coprocessor
  • STC - Store to coprocessor
  • MCR - Move to coprocessor
  • MRC - Move from coprocessor

Arithmetics:

  • MUL - Multiplication
  • MLA - Multiplication and accumulate

Block Diagram

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Core

Pipeline

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Die

All ARM2 Chips

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References

  • Furber, S. B., and A. R. Wilson. "The Acorn RISC Machine ߞ an architectural view." Electronics and Power 33.6 (1987): 402-405.
codenameARM2 +
core count1 +
designerARM Holdings +
first launched1986 +
full page nameacorn/microarchitectures/arm2 +
instance ofmicroarchitecture +
instruction set architectureARMv2 +
manufacturerVLSI Technology + and Sanyo +
microarchitecture typeCPU +
nameARM2 +
pipeline stages3 +
process2,000 nm (2 μm, 0.002 mm) +