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From WikiChip
Difference between revisions of "acorn/microarchitectures/arm2"
< acorn
| Line 5: | Line 5: | ||
|designer=ARM Holdings | |designer=ARM Holdings | ||
|manufacturer=VLSI Technology | |manufacturer=VLSI Technology | ||
| + | |manufacturer 2=Sanyo | ||
|introduction=1986 | |introduction=1986 | ||
|process=2 µm | |process=2 µm | ||
Revision as of 00:09, 28 June 2017
| Edit Values | |
| ARM2 µarch | |
| General Info | |
| Arch Type | CPU |
| Designer | ARM Holdings |
| Manufacturer | VLSI Technology, Sanyo |
| Introduction | 1986 |
| Process | 2 µm |
| Core Configs | 1 |
| Pipeline | |
| Type | Scalar, Pipelined |
| Stages | 3 |
| Decode | 1-way |
| Instructions | |
| ISA | ARMv2 |
| Cache | |
| L1I Cache | 0 KiB/Core |
| L1D Cache | 0 KiB/Core |
| Succession | |
Retrieved from "https://en.wikichip.org/w/index.php?title=acorn/microarchitectures/arm2&oldid=48493"
Facts about "ARM2 - Microarchitectures - Acorn"
| codename | ARM2 + |
| core count | 1 + |
| designer | ARM Holdings + |
| first launched | 1986 + |
| full page name | acorn/microarchitectures/arm2 + |
| instance of | microarchitecture + |
| instruction set architecture | ARMv2 + |
| manufacturer | VLSI Technology + and Sanyo + |
| microarchitecture type | CPU + |
| name | ARM2 + |
| pipeline stages | 3 + |
| process | 2,000 nm (2 μm, 0.002 mm) + |
