Semiconductor & Computer Engineering
From WikiChip
Difference between revisions of "Template:x86 isa main"
| (4 intermediate revisions by 2 users not shown) | |||
| Line 14: | Line 14: | ||
* {{x86|Model-Specific Register}} | * {{x86|Model-Specific Register}} | ||
* {{x86|Assembly}} | * {{x86|Assembly}} | ||
| − | |||
* {{x86|Interrupts}} | * {{x86|Interrupts}} | ||
* {{x86|Micro-Ops}} | * {{x86|Micro-Ops}} | ||
| Line 20: | Line 19: | ||
* {{x86|Calling Convention}} | * {{x86|Calling Convention}} | ||
* {{x86|Microarchitectures}} | * {{x86|Microarchitectures}} | ||
| + | * {{x86|CPUID}} | ||
| + | <div class="header">CPUIDs</div> | ||
| + | * {{amd|CPUID|AMD's CPUIDs}} | ||
| + | * {{intel|CPUID|Intel's CPUIDs}} | ||
<div class="header">Modes</div> | <div class="header">Modes</div> | ||
* {{x86|Real Mode|Real}} | * {{x86|Real Mode|Real}} | ||
| Line 30: | Line 33: | ||
* {{x86|ADX}} | * {{x86|ADX}} | ||
* {{x86|AES}} | * {{x86|AES}} | ||
| + | * {{x86|AMX}} | ||
* {{x86|AVX}} | * {{x86|AVX}} | ||
* {{x86|AVX2}} | * {{x86|AVX2}} | ||
| Line 45: | Line 49: | ||
* {{x86|MMX}} | * {{x86|MMX}} | ||
* {{x86|MPX}} | * {{x86|MPX}} | ||
| + | * {{x86|persistent memory extensions|PMEM}} | ||
* {{x86|PREFETCH}} | * {{x86|PREFETCH}} | ||
* {{x86|RdRAND}} | * {{x86|RdRAND}} | ||
| Line 66: | Line 71: | ||
* {{x86|TSX}} | * {{x86|TSX}} | ||
* {{x86|XOP}} | * {{x86|XOP}} | ||
| − | </div> | + | </div>{{Navbar|Template:x86 isa main|text=|mini=1|style=float:right;}} |
| − | {{Navbar|Template:x86 isa main|text=|mini=1|style=float:right;}} | ||
</div> | </div> | ||
Latest revision as of 23:37, 28 June 2020
x86
Instruction Set Architecture
Instruction Set Architecture
General
Variants
Topics
- Instructions
- Addressing Modes
- Registers
- Model-Specific Register
- Assembly
- Interrupts
- Micro-Ops
- Timer
- Calling Convention
- Microarchitectures
- CPUID
CPUIDs
Modes
Extensions(all)
