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Difference between revisions of "Template:x86 features"

(+tme/mktme)
(Updated AVX-512 links.)
 
(2 intermediate revisions by one other user not shown)
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-->{{#if: {{istrue|{{{sse42|}}}}} | <tr><th style="width: 100px;">SSE4.2</th><td>{{x86|SSE4.2|Streaming SIMD Extensions 4.2}}</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{sse42|}}}}} | <tr><th style="width: 100px;">SSE4.2</th><td>{{x86|SSE4.2|Streaming SIMD Extensions 4.2}}</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{sse4a|}}}}} | <tr><th style="width: 100px;">SSE4a</th><td>{{x86|SSE4a|Streaming SIMD Extensions 4a}}</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{sse4a|}}}}} | <tr><th style="width: 100px;">SSE4a</th><td>{{x86|SSE4a|Streaming SIMD Extensions 4a}}</td></tr> }}<!--
-->{{#if: {{istrue|{{{sse_gfni|}}}}} | <tr><th style="width: 100px;">SSE_GFNI</th><td>{{x86|SSE Galois Field New Instructions}}</td></tr> }}<!--
+
-->{{#if: {{istrue|{{{sse_gfni|}}}}} | <tr><th style="width: 100px;">GFNI</th><td>{{x86|GFNI|SSE Galois Field New Instructions}}</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{avx|}}}}} | <tr><th style="width: 100px;">AVX</th><td>{{x86|AVX|Advanced Vector Extensions}}</td></tr>[[has feature::Advanced Vector Extensions| ]][[has advanced vector extensions::true| ]] }}<!--
 
-->{{#if: {{istrue|{{{avx|}}}}} | <tr><th style="width: 100px;">AVX</th><td>{{x86|AVX|Advanced Vector Extensions}}</td></tr>[[has feature::Advanced Vector Extensions| ]][[has advanced vector extensions::true| ]] }}<!--
-->{{#if: {{istrue|{{{avx_gfni|}}}}} | <tr><th style="width: 100px;">AVX_GFNI</th><td>{{x86|AVX Galois Field New Instructions}}</td></tr> }}<!--
+
-->{{#if: {{istrue|{{{avx_gfni|}}}}} | <tr><th style="width: 100px;">AVX+GFNI</th><td>{{x86|GFNI|AVX Galois Field New Instructions}}</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{avx2|}}}}} | <tr><th style="width: 100px;">AVX2</th><td>{{x86|AVX2|Advanced Vector Extensions 2}}</td></tr>[[has feature::Advanced Vector Extensions 2| ]][[has advanced vector extensions 2::true| ]] }}<!--
 
-->{{#if: {{istrue|{{{avx2|}}}}} | <tr><th style="width: 100px;">AVX2</th><td>{{x86|AVX2|Advanced Vector Extensions 2}}</td></tr>[[has feature::Advanced Vector Extensions 2| ]][[has advanced vector extensions 2::true| ]] }}<!--
 
-->{{#if: {{istrue|{{{avx512f|{{{avx512cd|{{{avx512er|{{{avx512pf|{{{avx512bw|{{{avx512dq|{{{avx512vl|{{{avx512ifma|{{{avx512vbmi|{{{avx5124fmaps|{{{avx5124vnniw|{{{avx512vpopcntdq|{{{avx512vnni|{{{avx512gfni|{{{avx512vaes|{{{avx512vbmi2|{{{avx512bitalg|{{{avx512vpclmulqdq|{{{sse_gfni|{{{avx_gfni}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}} | <tr><th style="width: 100px;">AVX-512</th><td>{{x86|avx-512|Advanced Vector 512-bit}} {{#if: {{{avx512units|}}}|([[number of avx-512 execution units::{{{avx512units}}}]] Unit{{#ifexpr: {{{avx512units}}} > 1|s}})}}</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{avx512f|{{{avx512cd|{{{avx512er|{{{avx512pf|{{{avx512bw|{{{avx512dq|{{{avx512vl|{{{avx512ifma|{{{avx512vbmi|{{{avx5124fmaps|{{{avx5124vnniw|{{{avx512vpopcntdq|{{{avx512vnni|{{{avx512gfni|{{{avx512vaes|{{{avx512vbmi2|{{{avx512bitalg|{{{avx512vpclmulqdq|{{{sse_gfni|{{{avx_gfni}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}}} | <tr><th style="width: 100px;">AVX-512</th><td>{{x86|avx-512|Advanced Vector 512-bit}} {{#if: {{{avx512units|}}}|([[number of avx-512 execution units::{{{avx512units}}}]] Unit{{#ifexpr: {{{avx512units}}} > 1|s}})}}</td></tr> }}<!--
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-->{{#if: {{istrue|{{{avx512pf|}}}}} | <tr><th style="width: 100px;">AVX512PF</th><td>AVX-512 Prefetch</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{avx512pf|}}}}} | <tr><th style="width: 100px;">AVX512PF</th><td>AVX-512 Prefetch</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{avx512bw|}}}}} | <tr><th style="width: 100px;">AVX512BW</th><td>AVX-512 Byte and Word</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{avx512bw|}}}}} | <tr><th style="width: 100px;">AVX512BW</th><td>AVX-512 Byte and Word</td></tr> }}<!--
-->{{#if: {{istrue|{{{avx512dq|}}}}} | <tr><th style="width: 100px;">AVX512DQ</th><td>AVX-512 Double and Quad</td></tr> }}<!--
+
-->{{#if: {{istrue|{{{avx512dq|}}}}} | <tr><th style="width: 100px;">AVX512DQ</th><td>{{x86|AVX512DQ|AVX-512 Doubleword and Quadword Instructions}}</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{avx512vl|}}}}} | <tr><th style="width: 100px;">AVX512VL</th><td>AVX-512 Vector Length</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{avx512vl|}}}}} | <tr><th style="width: 100px;">AVX512VL</th><td>AVX-512 Vector Length</td></tr> }}<!--
-->{{#if: {{istrue|{{{avx512ifma|}}}}} | <tr><th style="width: 100px;">AVX512IFMA</th><td>AVX-512 Integer Fused Multiply-Add</td></tr> }}<!--
+
-->{{#if: {{istrue|{{{avx512ifma|}}}}} | <tr><th style="width: 100px;">AVX512_IFMA</th><td>{{x86|AVX512_IFMA|AVX-512 Integer Fused Multiply-Add}}</td></tr> }}<!--
-->{{#if: {{istrue|{{{avx512vbmi|}}}}} | <tr><th style="width: 100px;">AVX512VBMI</th><td>AVX-512 Vector Bit Manipulation</td></tr> }}<!--
+
-->{{#if: {{istrue|{{{avx512vbmi|}}}}} | <tr><th style="width: 100px;">AVX512_VBMI</th><td>{{x86|AVX512_VBMI|AVX-512 Vector Bit Manipulation Instructions}}</td></tr> }}<!--
-->{{#if: {{istrue|{{{avx5124fmaps|}}}}} | <tr><th style="width: 100px;">AVX5124FMAPS</th><td>AVX-512 Fused Multiply Accumulation Packed Single precision</td></tr> }}<!--
+
-->{{#if: {{istrue|{{{avx5124fmaps|}}}}} | <tr><th style="width: 100px;">AVX512_4FMAPS</th><td>{{x86|AVX512_4FMAPS|AVX-512 Fused Multiply-Accumulate Packed Single Precision}}</td></tr> }}<!--
-->{{#if: {{istrue|{{{avx512vnni|}}}}} | <tr><th style="width: 100px;">AVX512VNNI</th><td>{{x86|avx512vnni|AVX-512 Vector Neural Network Instructions}}</td></tr> }}<!--
+
-->{{#if: {{istrue|{{{avx512vnni|}}}}} | <tr><th style="width: 100px;">AVX512_VNNI</th><td>{{x86|AVX512_VNNI|AVX-512 Vector Neural Network Instructions}}</td></tr> }}<!--
-->{{#if: {{istrue|{{{avx5124vnniw|}}}}} | <tr><th style="width: 100px;">AVX5124VNNIW</th><td>AVX-512 Vector Neural Network Instructions Word Variable Precision</td></tr> }}<!--
+
-->{{#if: {{istrue|{{{avx5124vnniw|}}}}} | <tr><th style="width: 100px;">AVX512_4VNNIW</th><td>{{x86|AVX512_4VNNIW|AVX-512 Vector Neural Network Instructions Word Variable Precision}}</td></tr> }}<!--
-->{{#if: {{istrue|{{{avx512vpopcntdq|}}}}} | <tr><th style="width: 100px;">AVX512VPOPCNTDQ</th><td>AVX-512 Vector Population Count Doubleword and Quadword </td></tr> }}<!--
+
-->{{#if: {{istrue|{{{avx512vpopcntdq|}}}}} | <tr><th style="width: 100px;">AVX512_VPOPCNTDQ</th><td>{{x86|AVX512_VPOPCNTDQ|AVX-512 Vector Population Count Doubleword and Quadword}}</td></tr> }}<!--
-->{{#if: {{istrue|{{{avx512gfni|}}}}} | <tr><th style="width: 100px;">AVX512GFNI</th><td>AVX-512 Galois Field New Instructions </td></tr> }}<!--
+
-->{{#if: {{istrue|{{{avx512gfni|}}}}} | <tr><th style="width: 100px;">AVX512F+GFNI</th><td>{{x86|GFNI|AVX-512 Galois Field New Instructions}}</td></tr> }}<!--
-->{{#if: {{istrue|{{{avx512vaes|}}}}} | <tr><th style="width: 100px;">AVX512VAES</th><td>AVX-512 Vector AES </td></tr> }}<!--
+
-->{{#if: {{istrue|{{{avx512vaes|}}}}} | <tr><th style="width: 100px;">AVX512F+VAES</th><td>{{x86|VAES|AVX-512 Vector AES Instructions}}</td></tr> }}<!--
-->{{#if: {{istrue|{{{avx512vbmi2|}}}}} | <tr><th style="width: 100px;">AVX512VBMI2</th><td>AVX-512 Vector Bit Manipulation, Version 2 </td></tr> }}<!--
+
-->{{#if: {{istrue|{{{avx512vbmi2|}}}}} | <tr><th style="width: 100px;">AVX512_VBMI2</th><td>{{x86|AVX512_VBMI2|AVX-512 Vector Bit Manipulation Instructions 2}}</td></tr> }}<!--
-->{{#if: {{istrue|{{{avx512bitalg|}}}}} | <tr><th style="width: 100px;">AVX512BITALG</th><td>AVX-512 Bit Algorithms </td></tr> }}<!--
+
-->{{#if: {{istrue|{{{avx512bitalg|}}}}} | <tr><th style="width: 100px;">AVX512_BITALG</th><td>{{x86|AVX512_BITALG|AVX-512 Bit Algorithms}}</td></tr> }}<!--
-->{{#if: {{istrue|{{{avx512vpclmulqdq|}}}}} | <tr><th style="width: 100px;">AVX512VPCLMULQDQ</th><td>AVX-512 Vector Carry-less Multiply </td></tr> }}<!--
+
-->{{#if: {{istrue|{{{avx512vpclmulqdq|}}}}} | <tr><th style="width: 100px;">AVX512F+VPCLMULQDQ</th><td>{{x86|VPCLMULQDQ|Vector Carry-Less Multiplication of Quadwords}}</td></tr> }}<!--
 +
-->{{#if: {{istrue|{{{bfloat16|}}}}} | <tr><th style="width: 100px;">AVX512_BF16</th><td>{{x86|AVX512_BF16|AVX-512 BFloat16 Instructions}}</td></tr>}}<!--
 
-->{{#if: {{istrue|{{{abm|}}}}} | <tr><th style="width: 100px;">ABM</th><td>{{x86|ABM|Advanced Bit Manipulation}}</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{abm|}}}}} | <tr><th style="width: 100px;">ABM</th><td>{{x86|ABM|Advanced Bit Manipulation}}</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{tbm|}}}}} | <tr><th style="width: 100px;">TBM</th><td>{{x86|TBM|Trailing Bit Manipulation}}</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{tbm|}}}}} | <tr><th style="width: 100px;">TBM</th><td>{{x86|TBM|Trailing Bit Manipulation}}</td></tr> }}<!--
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-->{{#if: {{istrue|{{{clmul|}}}}} | <tr><th style="width: 100px;">CLMUL</th><td>{{x86|CLMUL|Carry-less Multiplication Extension}}</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{clmul|}}}}} | <tr><th style="width: 100px;">CLMUL</th><td>{{x86|CLMUL|Carry-less Multiplication Extension}}</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{f16c|}}}}} | <tr><th style="width: 100px;">F16C</th><td>16-bit Floating Point Conversion</td></tr> }}<!--
 
-->{{#if: {{istrue|{{{f16c|}}}}} | <tr><th style="width: 100px;">F16C</th><td>16-bit Floating Point Conversion</td></tr> }}<!--
-->{{#if: {{istrue|{{{bfloat16|}}}}} | <tr><th style="width: 100px;">bfloat16</th><td>[[bfloat16|Brain floating-point format]]</td></tr> }}<!--
 
 
--></table>
 
--></table>
 
<table class="tl1" style="font-size: 0.9em; float: left; margin-right: 10px;"><!--
 
<table class="tl1" style="font-size: 0.9em; float: left; margin-right: 10px;"><!--
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-->{{#if: {{istrue|{{{amdpbod|}}}}} | <tr><th style="width: 100px;">PBO</th><td>{{amd|Precision Boost Overdrive}}</td></tr>[[has feature::Precision Boost Overdrive| ]][[has amd precision boost overdrive::true| ]] }}<!--
 
-->{{#if: {{istrue|{{{amdpbod|}}}}} | <tr><th style="width: 100px;">PBO</th><td>{{amd|Precision Boost Overdrive}}</td></tr>[[has feature::Precision Boost Overdrive| ]][[has amd precision boost overdrive::true| ]] }}<!--
 
-->{{#if: {{istrue|{{{intqat|}}}}} | <tr><th style="width: 100px;">QAT</th><td>Integrated {{intel|QuickAssist Technology}}</td></tr>[[has feature::Integrated QuickAssist Technology| ]][[has integrated intel quickassist technology::true| ]] }}<!--
 
-->{{#if: {{istrue|{{{intqat|}}}}} | <tr><th style="width: 100px;">QAT</th><td>Integrated {{intel|QuickAssist Technology}}</td></tr>[[has feature::Integrated QuickAssist Technology| ]][[has integrated intel quickassist technology::true| ]] }}<!--
-->{{#if: {{istrue|{{{tme|}}}}} | <tr><th style="width: 100px;">TME</th><td>Integrated {{intel|Total Memory Encryption}}</td></tr>[[has feature::Total Memory Encryption| ]][[has total memory encryption::true| ]] }}<!--
+
-->{{#if: {{istrue|{{{tme|}}}}} | <tr><th style="width: 100px;">TME</th><td>{{x86|Total Memory Encryption}}</td></tr>[[has feature::Total Memory Encryption| ]][[has total memory encryption::true| ]] }}<!--
-->{{#if: {{istrue|{{{mktme|}}}}} | <tr><th style="width: 100px;">MKTME</th><td>Integrated {{intel|Multi-Key Total Memory Encryption}}</td></tr>[[has feature::Multi-Key Total Memory Encryption| ]][[has multi-key total memory encryption::true| ]] }}<!--
+
-->{{#if: {{istrue|{{{mktme|}}}}} | <tr><th style="width: 100px;">MKTME</th><td>{{x86|Multi-Key Total Memory Encryption}}</td></tr>[[has feature::Multi-Key Total Memory Encryption| ]][[has multi-key total memory encryption::true| ]] }}<!--
 
--></table>
 
--></table>
 
</td>
 
</td>

Latest revision as of 17:18, 15 March 2023

[Edit/Modify Supported Features]

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Supported x86 Extensions & Processor Features