Semiconductor & Computer Engineering
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Difference between revisions of "Template:cache size"
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-->{{#if: {{{l2i cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L2I$</th><td style="min-width: 50px;">[[l2i$ size::{{{l2i cache}}}]]</td><td style="min-width: 75px;">{{{l2i break}}}</td><td style="min-width: 175px;">[[l2i$ description::{{{l2i desc}}}]]</td><td>{{#if:{{{l2i policy|}}}|{{{l2i policy}}}| }}</td></tr> }}<!-- | -->{{#if: {{{l2i cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L2I$</th><td style="min-width: 50px;">[[l2i$ size::{{{l2i cache}}}]]</td><td style="min-width: 75px;">{{{l2i break}}}</td><td style="min-width: 175px;">[[l2i$ description::{{{l2i desc}}}]]</td><td>{{#if:{{{l2i policy|}}}|{{{l2i policy}}}| }}</td></tr> }}<!-- | ||
-->{{#if: {{{l2d cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L2D$</th><td>[[l2d$ size::{{{l2d cache}}}]]</td><td style="min-width: 75px;">{{{l2d break}}}</td><td style="min-width: 175px;">{{#if: {{{l2d desc|}}} | [[l2d$ description::{{{l2d desc}}}]] | }}</td><td>{{#if:{{{l2d policy|}}}|{{{l2d policy}}}| }}</td></tr> }}<!-- | -->{{#if: {{{l2d cache|}}} | <tr><th style="text-align: center; min-width: 50px;">L2D$</th><td>[[l2d$ size::{{{l2d cache}}}]]</td><td style="min-width: 75px;">{{{l2d break}}}</td><td style="min-width: 175px;">{{#if: {{{l2d desc|}}} | [[l2d$ description::{{{l2d desc}}}]] | }}</td><td>{{#if:{{{l2d policy|}}}|{{{l2d policy}}}| }}</td></tr> }}<!-- | ||
| − | -->{{#if: {{#if: {{{l2i cache|}}}{{{l2d cache|}}}||1}} | <tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td style="min-width: 75px;">{{{l2 break}}}</td><td style="min-width: 175px;">{{#if: {{{l2 desc|}}} | [[l2$ description::{{{l2 desc}}}]] | }}</td><td>{{#if:{{{l2 policy|}}}|{{{l2 policy}}}| }}</td></tr> }}<!-- | + | -->{{#if: {{#if: {{{l2i cache|}}}{{{l2d cache|}}}||1}} | <tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td style="min-width: 75px;">{{{l2 break| }}}</td><td style="min-width: 175px;">{{#if: {{{l2 desc|}}} | [[l2$ description::{{{l2 desc}}}]] | }}</td><td>{{#if:{{{l2 policy|}}}|{{{l2 policy}}}| }}</td></tr> }}<!-- |
--></table></td></tr>{{#if: {{{l3 cache|}}}|<tr><td colspan="4"><hr></td></tr>}} }}<!-- | --></table></td></tr>{{#if: {{{l3 cache|}}}|<tr><td colspan="4"><hr></td></tr>}} }}<!-- | ||
-->{{#if: {{{l3 cache|}}} | <tr><th style="min-width: 35px;">L3$</th><td>[[l3$ size::{{{l3 cache}}}]]</td><td><table><tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td style="min-width: 75px;">{{#if:{{{l3 break|}}}|{{{l3 break}}}| }}</td><td style="min-width: 175px;">{{#if: {{{l3 desc|}}} | [[l3$ description::{{{l3 desc}}}]] | }}</td><td>{{#if:{{{l3 policy|}}}|{{{l3 policy}}}| }}</td></tr></table></td></tr>{{#if: {{{l4 cache|}}}|<tr><td colspan="4"><hr></td></tr>}} }}<!-- | -->{{#if: {{{l3 cache|}}} | <tr><th style="min-width: 35px;">L3$</th><td>[[l3$ size::{{{l3 cache}}}]]</td><td><table><tr><th style="text-align: center; min-width: 50px;"> </th><td style="min-width: 50px;"> </td><td style="min-width: 75px;">{{#if:{{{l3 break|}}}|{{{l3 break}}}| }}</td><td style="min-width: 175px;">{{#if: {{{l3 desc|}}} | [[l3$ description::{{{l3 desc}}}]] | }}</td><td>{{#if:{{{l3 policy|}}}|{{{l3 policy}}}| }}</td></tr></table></td></tr>{{#if: {{{l4 cache|}}}|<tr><td colspan="4"><hr></td></tr>}} }}<!-- | ||
Revision as of 15:45, 22 July 2017
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Cache Organization
Cache is a hardware component containing a relatively small and extremely fast memory designed to speed up the performance of a CPU by preparing ahead of time the data it needs to read from a relatively slower medium such as main memory. The organization and amount of cache can have a large impact on the performance, power consumption, die size, and consequently cost of the IC. Cache is specified by its size, number of sets, associativity, block size, sub-block size, and fetch and write-back policies. Note: All units are in kibibytes and mebibytes. |
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